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([2606:6d00:17:ebd3::c41]) by smtp.gmail.com with ESMTPSA id af79cd13be357-877796a1de6sm1488995285a.49.2025.10.07.11.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 11:06:08 -0700 (PDT) Message-ID: <3c62e3c837d534ef5bc21a95ec1dc408c38cb8a0.camel@ndufresne.ca> Subject: Re: [PATCH 00/16] media: platform: rga: Add RGA3 support From: Nicolas Dufresne To: Sven =?ISO-8859-1?Q?P=FCschel?= , Jacob Chen , Ezequiel Garcia , Mauro Carvalho Chehab , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de Date: Tue, 07 Oct 2025 14:06:06 -0400 In-Reply-To: <20251007-spu-rga3-v1-0-36ad85570402@pengutronix.de> References: <20251007-spu-rga3-v1-0-36ad85570402@pengutronix.de> Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-IcsCjmyMK96ZjT/TchVY" User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 --=-IcsCjmyMK96ZjT/TchVY Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, Le mardi 07 octobre 2025 =C3=A0 10:31 +0200, Sven P=C3=BCschel a =C3=A9crit= =C2=A0: > This series adds support for the Raster Graphic Acceleration 3 (RGA3) > peripheral, which is included in the RK3588 SoC. Unlike the RGA2 it > can use the existing rockchip-iommu-v2 driver to handle iommu mappings. > Also the RK3588 contains two independent RGA3 cores. Thanks for working on this. >=20 > Only scaling and format conversions between common 8bit RGB/YUV formats > are implemented. Also the color space conversion is fixed to BT601F. > This already allows a practical usage of the RGA3. This seems quite limiting, can we expect an update on this, can't be that h= ard to fully implement. >=20 > This was tested on a Radxa Rock 5T. With the increased clock speeds in > the devicetree around 160 fps were measured when scaling and converting This is quite vague, I've checked the patch and you didn't extend either th= ere. Is that an overclock or was it miss-configured ? Does RK implement a devfre= q ? Should that be moved with a voltage adjustement ? Is there any thermal near= by we should monitor ? > from RGBA 480x360 to NV12 3840x2160. Without the clock speed scaling a > default clock division factor of 2 is used and only around 80 fps are > reached with one core. The v4l2-compliance tests only complain about > the already failing colorspace propagation: Did you do any more format testing to validation all supported combinations= ? This is a tool [0] you can use to test this using GStreamer and how to use = it [1]. [0] https://gitlab.collabora.com/mediatek/aiot/lava-test-definitions/-/tree= /main/avvideocompare?ref_type=3Dheads [1] https://gitlab.collabora.com/mediatek/aiot/linux/-/blob/mediatek-next/.= gitlab-ci.yml?ref_type=3Dheads#L282 >=20 > =C2=A0 v4l2-compliance 1.28.1, 64 bits, 64-bit time_t > =C2=A0 ... > =C2=A0=C2=A0 fail: v4l2-test-formats.cpp(923): fmt_cap.g_colorspace() != =3D > col > =C2=A0=C2=A0 test VIDIOC_S_FMT: FAIL > =C2=A0 ... > =C2=A0 Total for rockchip-rga device /dev/video0: 47, Succeeded: 46, Fail= ed: 1, > Warnings: 0 >=20 > =C2=A0 v4l2-compliance 1.28.1, 64 bits, 64-bit time_t > =C2=A0 ... > =C2=A0=C2=A0 fail: v4l2-test-formats.cpp(923): fmt_cap.g_colorspace() != =3D > col > =C2=A0=C2=A0 test VIDIOC_S_FMT: FAIL > =C2=A0 ... > =C2=A0 Total for rockchip-rga device /dev/video1: 47, Succeeded: 46, Fail= ed: 1, > Warnings: 0 >=20 > =C2=A0 v4l2-compliance 1.28.1, 64 bits, 64-bit time_t > =C2=A0 ... > =C2=A0=C2=A0 fail: v4l2-test-formats.cpp(923): fmt_cap.g_colorspace() != =3D > col > =C2=A0=C2=A0 test VIDIOC_S_FMT: FAIL > =C2=A0 ... > =C2=A0 Total for rockchip-rga device /dev/video2: 47, Succeeded: 46, Fail= ed: 1, > Warnings: 0 >=20 > Each RGA core is a separate /dev/video device. To distinguish the RGA2 > core from the RGA3 cores the Card type is set accordingly. Combining all > cores into a single device and scheduling tasks to the best core might > be a future improvement, if it is desired by upstream to handle the > scheduling and selection in kernel space. It took me some time to understand why you spoke about multicore here. You forgot to say here that you add RGA3 into RGA2 driver. Some information on = why you went that path instead of a separate driver. =46rom high level view, I don't think its a good idea to multi-plex over heterogeneous core. They may not even produce the exact same pixels for the= same operation. They also don't share the same MMU, and at first glance, the use= of rkiommu in RGA3 means it can no longer handle CPU cache (though I don't kno= w if this is implemented/supported in upstream RGA2 driver). >=20 > Patch 1-2 are general cleanups > Patch 3-12 prepare the rga driver for the RGA3 > Patch 13 documments the RGA3 compatible value > Patch 14 adds the RGA3 cores to the rk3588 dtsi > Patch 15 increases the RGA3 core clock speeds > Patch 16 adds RGA3 support to the rga driver >=20 > Signed-off-by: Sven P=C3=BCschel > --- > Sven P=C3=BCschel (16): > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: use clk_bulk api > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: use stride for offse= t calculation > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: align stride to 16 b= ytes > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: move hw specific par= ts to a dedicated struct > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: use card type to spe= cify rga type > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: change offset to dma= _addresses > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: support external iom= mus > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: remove size from rga= _frame > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: remove stride from r= ga_frame > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: move rga_fmt to rga-= hw.h > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: add iommu restore fu= nction > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: handle error interru= pt > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: dt-bindings: media: rockchip-rga: a= dd rockchip,rk3588-rga3 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 arm64: dts: rockchip: add rga3 dt nodes > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 arm64: dts: rockchip: increase rga3 clock = speed > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 media: rockchip: rga: add rga3 support >=20 > =C2=A0.../devicetree/bindings/media/rockchip-rga.yaml=C2=A0=C2=A0=C2=A0 |= =C2=A0=C2=A0 1 + > =C2=A0arch/arm64/boot/dts/rockchip/rk3588-base.dtsi=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0 50 +++ > =C2=A0drivers/media/platform/rockchip/rga/Makefile=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 +- > =C2=A0drivers/media/platform/rockchip/rga/rga-buf.c=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0 78 ++-- > =C2=A0drivers/media/platform/rockchip/rga/rga-hw.c=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 | 356 ++++++++++++--- > =C2=A0drivers/media/platform/rockchip/rga/rga-hw.h=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0 15 +- > =C2=A0drivers/media/platform/rockchip/rga/rga.c=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 404 ++++++----------- > =C2=A0drivers/media/platform/rockchip/rga/rga.h=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 74 ++-- > =C2=A0drivers/media/platform/rockchip/rga/rga3-hw.c=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 | 490 > +++++++++++++++++++++ > =C2=A0drivers/media/platform/rockchip/rga/rga3-hw.h=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 | 186 ++++++++ > =C2=A010 files changed, 1246 insertions(+), 410 deletions(-) > --- > base-commit: afb100a5ea7a13d7e6937dcd3b36b19dc6cc9328 > change-id: 20251001-spu-rga3-8a00e018b120 >=20 > Best regards, --=-IcsCjmyMK96ZjT/TchVY Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTvDVKBFcTDwhoEbxLZQZRRKWBy9AUCaOVWjgAKCRDZQZRRKWBy 9MYwAQDAFCIsXy2vnCz1b/y+9mKp3XI/R9oRTPcTXia35pLGywD/SLpU/azQOYuj Eq4VTAEBMAbKxVFBtmRPL+5Gb/F4cAg= =pSPZ -----END PGP SIGNATURE----- --=-IcsCjmyMK96ZjT/TchVY--