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Tue, 24 Dec 2024 09:11:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BO9BI87004189 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Dec 2024 09:11:18 GMT Received: from [10.216.2.152] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Dec 2024 01:11:13 -0800 Message-ID: <3d37e1b2-a658-5de9-c575-6baf9cdaa40f@quicinc.com> Date: Tue, 24 Dec 2024 14:41:10 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v3 1/6] dt-bindings: PCI: Add binding for qps615 Content-Language: en-US To: Bjorn Helgaas CC: , Bjorn Helgaas , "Lorenzo Pieralisi" , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Konrad Dybcio , , Jingoo Han , Bartosz Golaszewski , , , , , References: <20241204212559.GA3007963@bhelgaas> From: Krishna Chaitanya Chundru In-Reply-To: <20241204212559.GA3007963@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: uszCFr4uBfXIdlltj5nTR6H3FjhTPJOb X-Proofpoint-GUID: uszCFr4uBfXIdlltj5nTR6H3FjhTPJOb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 clxscore=1015 suspectscore=0 phishscore=0 impostorscore=0 mlxscore=0 spamscore=0 adultscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412240077 On 12/5/2024 2:55 AM, Bjorn Helgaas wrote: > On Tue, Nov 12, 2024 at 08:31:33PM +0530, Krishna chaitanya chundru wrote: >> Add binding describing the Qualcomm PCIe switch, QPS615, >> which provides Ethernet MAC integrated to the 3rd downstream port >> and two downstream PCIe ports. > >> +$defs: >> + qps615-node: >> + type: object >> + >> + properties: >> + qcom,l0s-entry-delay-ns: >> + description: Aspm l0s entry delay. >> + >> + qcom,l1-entry-delay-ns: >> + description: Aspm l1 entry delay. > > To match spec usage: > s/Aspm/ASPM/ > s/l0s/L0s/ > s/l1/L1/ > > Other than the fact that qps615 needs the driver to configure these, > there's nothing qcom-specific here, so I suggest the names should omit > "qcom" and include "aspm". > >> + pcie { >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + pcie@0 { >> + device_type = "pci"; >> + reg = <0x0 0x0 0x0 0x0 0x0>; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges; >> + bus-range = <0x01 0xff>; >> + >> + pcie@0,0 { >> + compatible = "pci1179,0623"; >> + reg = <0x10000 0x0 0x0 0x0 0x0>; >> + device_type = "pci"; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges; >> + bus-range = <0x02 0xff>; > > This binding describes a switch. I don't think bus-range should > appear here at all because it is not a feature of the hardware (unless > the switch ports are broken and their Secondary/Subordinate Bus > Numbers are hard-wired). > > The Primary/Secondary/Subordinate Bus Numbers of all switch ports > should be writable and the PCI core knows how to manage them. > Bjorn, The dt binding check is throwing an error if we don't keep bus-range property for that reason we added it, from dt binding perspective i think it is mandatory to add this property. - Krishna Chaitanya. > Bjorn