Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller

["Arnd Bergmann" <arnd@arndb.de>]

On Wed, Oct 8, 2025, at 17:19, Manivannan Sadhasivam wrote:
> On Wed, Oct 08, 2025 at 10:35:34AM +0200, Arnd Bergmann wrote:
>> On Wed, Oct 8, 2025, at 10:26, Arnd Bergmann wrote:
>> > the physical addresses for RAM at 0x80000000 and on-chip devices
>> > at 0x40000000. This probably works fine as long as the total
>> > PCI memory space assignment stays below 0x40000000 but would
>> > fail once addresses actually start clashing.
>> 
>> I got confused here myself, but what I should have said is that
>> having the DMA address for the RAM overlap the BAR space
>> as seen from PCI is problematic as the PCI host bridge
>> cannot tell PCI P2P transfers from DMA to RAM, so one
>> of them will be broken here.
>> 
>
> No. The IP just sets up the outbound mapping here for the entire 'ranges'. When
> P2P happens, it will use the inbound mapping translation.

That is not my impression from reading the code: At least for
the case where both devices are on the same bridge and they
use map_type=PCI_P2PDMA_MAP_BUS_ADDR, I would expect the DMA
to use the plain PCI bus address, not going through the
dma-ranges+ranges translation that would apply when they are
on different host bridges.

> So your concern would be valid if the 'dma-ranges' (for which inbound
> translation happens) overlapped with the RAM/MMIO range. But that is not the
> case here.

dma-ranges should normally list all the memory controllers, so in
this case at least the 0x80000000..0xffffffff range of PCI bus
addresses must be routed from the host bridge to RAM. If a BAR
is assigned to the same numbers, I would expect a PCI bridge
to direct a DMA transfer downstream to that BAR instead
of upstream to the CPU even before it gets to the host bridge.

      Arnd