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From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
To: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	agross@kernel.org, bjorn.andersson@linaro.org,
	robh+dt@kernel.org, krzk+dt@kernel.org,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
Cc: dmitry.baryshkov@linaro.org, jonathan@marek.ca, hfink@snap.com,
	jgrahsl@snap.com
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sm8250: camss: Add CAMSS block definition
Date: Fri, 15 Apr 2022 00:03:59 +0100	[thread overview]
Message-ID: <3da19aeb-a79e-3d64-7c64-891af2cbb392@linaro.org> (raw)
In-Reply-To: <13ad033e-cd5d-3a8c-b036-50a3ac4245c0@linaro.org>

On 14/04/2022 08:45, Vladimir Zapolskiy wrote:
> Hi Bryan,
> 
> On 4/14/22 02:17, Bryan O'Donoghue wrote:
>> Adds a CAMSS definition block.
>>
>> Co-developed-by: Julian Grahsl <jgrahsl@snap.com>
>> Signed-off-by: Julian Grahsl <jgrahsl@snap.com>
>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 153 +++++++++++++++++++++++++++
>>   1 file changed, 153 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi 
>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index 906bc8ed25b7..c69a8a88657a 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -3150,6 +3150,159 @@ videocc: clock-controller@abf0000 {
>>               #power-domain-cells = <1>;
>>           };
>> +        camss: camss@ac6a000 {
>> +            compatible = "qcom,sm8250-camss";
>> +            status = "disabled";
>> +
>> +            reg = <0 0xac6a000 0 0x2000>,
>> +                  <0 0xac6c000 0 0x2000>,
>> +                  <0 0xac6e000 0 0x1000>,
>> +                  <0 0xac70000 0 0x1000>,
>> +                  <0 0xac72000 0 0x1000>,
>> +                  <0 0xac74000 0 0x1000>,
>> +                  <0 0xacb4000 0 0xd000>,
>> +                  <0 0xacc3000 0 0xd000>,
>> +                  <0 0xacd9000 0 0x2200>,
>> +                  <0 0xacdb200 0 0x2200>;
>> +            reg-names = "csiphy0",
>> +                    "csiphy1",
>> +                    "csiphy2",
>> +                    "csiphy3",
>> +                    "csiphy4",
>> +                    "csiphy5",
>> +                    "vfe0",
>> +                    "vfe1",
>> +                    "vfe_lite0",
>> +                    "vfe_lite1";
>> +
>> +            interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
>> +            interrupt-names = "csiphy0",
>> +                      "csiphy1",
>> +                      "csiphy2",
>> +                      "csiphy3",
>> +                      "csiphy4",
>> +                      "csiphy5",
>> +                      "csid0",
>> +                      "csid1",
>> +                      "csid2",
>> +                      "csid3",
>> +                      "vfe0",
>> +                      "vfe1",
>> +                      "vfe_lite0",
>> +                      "vfe_lite1";
>> +
>> +            power-domains = <&camcc IFE_0_GDSC>,
>> +                    <&camcc IFE_1_GDSC>,
>> +                    <&camcc TITAN_TOP_GDSC>;
>> +
> 
> do you need to add 'power-domain-names' property here as well?

I looked at this, I don't believe camss depends on it, sdm845 since it 
does dev_pm_domain_attach_by_id() instead of dev_pm_domain_attach_by_name()
> 
>> +            interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc 
>> SLAVE_CAMERA_CFG>,
>> +                    <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
>> +                    <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
>> +                    <&mmss_noc MASTER_CAMNOC_ICP &mc_virt 
>> SLAVE_EBI_CH0>;
> 
> Recently there was a discussion on the list that interconnects are 2-cells,
> if so, the array above should be updated accordingly.

Hmm. The above NOC nodes are declared <1> for me, I'll look into this 
some more though.

  reply	other threads:[~2022-04-14 23:04 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-13 23:17 [PATCH v2 0/3] Add camss to SM8250 dtsi Bryan O'Donoghue
2022-04-13 23:17 ` [PATCH v2 1/3] arm64: dts: qcom: sm8250: Add camcc DT node Bryan O'Donoghue
2022-04-14  7:41   ` Vladimir Zapolskiy
2022-04-14 23:05     ` Bryan O'Donoghue
2022-04-13 23:17 ` [PATCH v2 2/3] arm64: dts: qcom: sm8250: camss: Add CAMSS block definition Bryan O'Donoghue
2022-04-14  7:45   ` Vladimir Zapolskiy
2022-04-14 23:03     ` Bryan O'Donoghue [this message]
2022-04-13 23:17 ` [PATCH v2 3/3] arm64: dts: qcom: sm8250: camss: Add CCI definitions Bryan O'Donoghue
2022-04-14  7:49   ` Vladimir Zapolskiy
2022-04-13 23:23 ` [PATCH v2 0/3] Add camss to SM8250 dtsi Bryan O'Donoghue

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