Re: [PATCH RFC v6 0/7] Add support for Adreno 810 GPU

[Akhil P Oommen <akhilpo@oss.qualcomm.com>]

On 5/15/2026 10:38 AM, Alexander Koskovich wrote:
> Adreno 810 is present in the Milos SoC and is the first GPU to be released in
> the A8x family.
> 
> This series is marked as RFC because it depends on a few other in review
> series, GPU GX GDSC handling [1], QFPROM efuse for Milos [2], and devicetree
> support for Glymur [3] (for a8xx RSCC offset fix and X2-185 bindings change).
> 
> Also depends on the GXCLKCTL block for Milos [4], but this is no longer in
> review and has been applied.
> 
> [1]: https://lore.kernel.org/linux-arm-msm/20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com
> [2]: https://lore.kernel.org/linux-arm-msm/20260331-milos-qfprom-v1-0-36017cc642db@pm.me
> [3]: https://lore.kernel.org/linux-arm-msm/20260513-glymur-gpu-dt-v4-0-f83832c3bc9a@oss.qualcomm.com
> [4]: https://lore.kernel.org/linux-arm-msm/20260417-milos-gxclkctl-v3-0-08f5988c43a2@fairphone.com
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

For the rest of the patches that doesn't have my R-b tag in this series.

-Akhil

> ---
> Changes in v6:
> - Re-jigged the register ranges for GPU/GMU to match Glymur
> - Depend on RSCC offset fix
> - Fix bindings to add constraints for reg list
> - Link to v5: https://lore.kernel.org/r/20260502-adreno-810-v5-0-bc9fd2bb788d@pm.me
> 
> Changes in v5:
> - Sync with latest kgsl
> - Link to v4: https://lore.kernel.org/r/20260416-adreno-810-v4-0-61676e073f8a@pm.me
> 
> Changes in v4:
> - Add 1150MHz speedbin
> - Rebase on next-20260415
> - Add dep on efuse patchset
> - Link to v3: https://lore.kernel.org/r/20260407-adreno-810-v3-0-30cb7f196ed4@pm.me
> 
> Changes in v3:
> - Drop DEMET from GMU clocks (not required on A810)
> - Document qcom,adreno-44010000 compatible (regex is gone in 7.0+)
> - Drop zeroed out CP_PROTECT_REG[46, 62] range, not required
> - Add a810_protect to __build_asserts
> - Add UCHE_CCHE_TRAP_BASE_[LO|HI] and UCHE_CCHE_WRITE_THRU_BASE_[LO|HI] to a810_pwrup_reglist_regs
> - Move TPL1 registers to a810_pwrup_reglist_regs
> - Include all protect registers in a810_ifpc_reglist_regs
> - Revert pipe reg comment, just copied it from downstream but original also works
> - Link to v2: https://lore.kernel.org/r/20260402-adreno-810-v2-0-ce337ca87a9e@pm.me
> 
> Changes in v2:
> - Mark as RFC due to dependency on in-review changes
> - Explain in DTS commit why qcom,kaanapali-gxclkctl.h and not qcom,milos-gxclkctl.h
> - cx_mmio -> cx_misc_mmio
> - Sync a810_nonctxt_regs with GRAPHICS.LA.14.0.r5-03100-lanai.0
> - Link to v1: https://lore.kernel.org/r/20260331-adreno-810-v1-0-725801dbb12b@pm.me
> 
> ---
> Alexander Koskovich (7):
>       dt-bindings: display/msm/gmu: Document Adreno 810 GMU
>       dt-bindings: display/msm/gpu: Document Adreno 810 GPU
>       drm/msm/adreno: rename llc_mmio to cx_misc_mmio
>       drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC
>       drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature
>       drm/msm/adreno: add Adreno 810 GPU support
>       arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes
> 
>  .../devicetree/bindings/display/msm/gmu.yaml       |  30 +++
>  .../devicetree/bindings/display/msm/gpu.yaml       |   5 +-
>  arch/arm64/boot/dts/qcom/milos.dtsi                | 165 ++++++++++++
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c          | 298 +++++++++++++++++++++
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c              |   8 +-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c              |  44 ++-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h              |  14 +-
>  drivers/gpu/drm/msm/adreno/a8xx_gpu.c              |   6 +-
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h            |   5 +
>  9 files changed, 536 insertions(+), 39 deletions(-)
> ---
> base-commit: 2ca0470eca8b4cee27aeeb39bd93c1f4c96b7e7b
> change-id: 20260330-adreno-810-5a47525522cd
> 
> Best regards,