From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5055BC433EF for ; Wed, 18 May 2022 04:25:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229806AbiEREZF (ORCPT ); Wed, 18 May 2022 00:25:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229677AbiEREZE (ORCPT ); Wed, 18 May 2022 00:25:04 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75335326CD; Tue, 17 May 2022 21:25:02 -0700 (PDT) X-UUID: c9b7ad4095c84559b58e19bb7ac77634-20220518 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:92fa0d12-539f-4c30-89ed-7a5271ff7ebf,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:20,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:70 X-CID-INFO: VERSION:1.1.5,REQID:92fa0d12-539f-4c30-89ed-7a5271ff7ebf,OB:0,LOB: 0,IP:0,URL:5,TC:0,Content:20,EDM:0,RT:0,SF:45,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:70 X-CID-META: VersionHash:2a19b09,CLOUDID:db6e95e2-edbf-4bd4-8a34-dfc5f7bb086d,C OID:30f6d911fb82,Recheck:0,SF:28|17|19|48,TC:nil,Content:3,EDM:-3,IP:nil,U RL:1,File:nil,QS:0,BEC:nil X-UUID: c9b7ad4095c84559b58e19bb7ac77634-20220518 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1458528257; Wed, 18 May 2022 12:24:57 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 18 May 2022 12:24:56 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 18 May 2022 12:24:55 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 18 May 2022 12:24:55 +0800 Message-ID: <3dc39acc0fae4045f7513a71432f99b66fdf9f99.camel@mediatek.com> Subject: Re: [PATCH v6 1/4] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml From: CK Hu To: Rex-BC Chen , , , , CC: , , , , , , , , , Date: Wed, 18 May 2022 12:24:55 +0800 In-Reply-To: <20220504091923.2219-2-rex-bc.chen@mediatek.com> References: <20220504091923.2219-1-rex-bc.chen@mediatek.com> <20220504091923.2219-2-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, Rex: On Wed, 2022-05-04 at 17:19 +0800, Rex-BC Chen wrote: > From: Xinlei Lee > > Convert mediatek,dsi.txt to mediatek,dsi.yaml format Reviewed-by: CK Hu > > Signed-off-by: Xinlei Lee > Signed-off-by: Rex-BC Chen > --- > .../display/mediatek/mediatek,dsi.txt | 62 ---------- > .../display/mediatek/mediatek,dsi.yaml | 115 > ++++++++++++++++++ > 2 files changed, 115 insertions(+), 62 deletions(-) > delete mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > deleted file mode 100644 > index 36b01458f45c..000000000000 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ /dev/null > @@ -1,62 +0,0 @@ > -Mediatek DSI Device > -=================== > - > -The Mediatek DSI function block is a sink of the display subsystem > and can > -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for > dual- > -channel output. > - > -Required properties: > -- compatible: "mediatek,-dsi" > -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. > -- reg: Physical base address and length of the controller's > registers > -- interrupts: The interrupt signal from the function block. > -- clocks: device clocks > - See Documentation/devicetree/bindings/clock/clock-bindings.txt for > details. > -- clock-names: must contain "engine", "digital", and "hs" > -- phys: phandle link to the MIPI D-PHY controller. > -- phy-names: must contain "dphy" > -- port: Output port node with endpoint definitions as described in > - Documentation/devicetree/bindings/graph.txt. This port should be > connected > - to the input port of an attached DSI panel or DSI-to-eDP encoder > chip. > - > -Optional properties: > -- resets: list of phandle + reset specifier pair, as described in > [1]. > - > -[1] Documentation/devicetree/bindings/reset/reset.txt > - > -MIPI TX Configuration Module > -============================ > - > -See phy/mediatek,dsi-phy.yaml > - > -Example: > - > -mipi_tx0: mipi-dphy@10215000 { > - compatible = "mediatek,mt8173-mipi-tx"; > - reg = <0 0x10215000 0 0x1000>; > - clocks = <&clk26m>; > - clock-output-names = "mipi_tx0_pll"; > - #clock-cells = <0>; > - #phy-cells = <0>; > - drive-strength-microamp = <4600>; > - nvmem-cells= <&mipi_tx_calibration>; > - nvmem-cell-names = "calibration-data"; > -}; > - > -dsi0: dsi@1401b000 { > - compatible = "mediatek,mt8173-dsi"; > - reg = <0 0x1401b000 0 0x1000>; > - interrupts = ; > - clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > - <&mipi_tx0>; > - clock-names = "engine", "digital", "hs"; > - resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > - phys = <&mipi_tx0>; > - phy-names = "dphy"; > - > - port { > - dsi0_out: endpoint { > - remote-endpoint = <&panel_in>; > - }; > - }; > -}; > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > new file mode 100644 > index 000000000000..fa5bdf28668a > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yam > l > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml*__;Iw!!CTRNKA9wMg0ARbw!zKJCSsOqM0Bn_efj50JX_HvOItJ8ZUdgh54drCoUdMkmnmVb5pH4pd-gj5RZUQ$ > > +$schema: > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zKJCSsOqM0Bn_efj50JX_HvOItJ8ZUdgh54drCoUdMkmnmVb5pH4pd8zHOMcVQ$ > > + > +title: MediaTek DSI Controller Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu > + - Philipp Zabel > + - Jitao Shi > + - Xinlei Lee > + > +description: | > + The MediaTek DSI function block is a sink of the display subsystem > and can > + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized > for dual- > + channel output. > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-dsi > + - mediatek,mt7623-dsi > + - mediatek,mt8167-dsi > + - mediatek,mt8173-dsi > + - mediatek,mt8183-dsi > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: Engine Clock > + - description: Digital Clock > + - description: HS Clock > + > + clock-names: > + items: > + - const: engine > + - const: digital > + - const: hs > + > + resets: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: dphy > + > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output port node. This port should be connected to the input > + port of an attached DSI panel or DSI-to-eDP encoder chip. > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - clocks > + - clock-names > + - phys > + - phy-names > + - port > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + dsi0: dsi@14014000 { > + compatible = "mediatek,mt8183-dsi"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DSI0_MM>, > + <&mmsys CLK_MM_DSI0_IF>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + port { > + dsi0_out: endpoint { > + remote-endpoint = <&panel_in>; > + }; > + }; > + }; > + }; > + > +...