From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add PLL clock node
Date: Thu, 23 Feb 2023 10:04:50 +0100 [thread overview]
Message-ID: <3dd8c78b-20ea-24c8-4019-cc03ebbcad71@linaro.org> (raw)
In-Reply-To: <84a785bb-8a48-fa55-ea64-29c21ac42cf8@starfivetech.com>
On 23/02/2023 10:03, Xingyu Wu wrote:
> On 2023/2/23 16:52, Krzysztof Kozlowski wrote:
>> On 23/02/2023 09:47, Xingyu Wu wrote:
>>> On 2023/2/22 17:09, Krzysztof Kozlowski wrote:
>>>> On 21/02/2023 15:11, Xingyu Wu wrote:
>>>>> Add the PLL clock node for the Starfive JH7110 SoC and
>>>>> modify the SYSCRG node to add PLL clocks.
>>>>>
>>>>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>>>>> ---
>>>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++--
>>>>> 1 file changed, 13 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>>> index b6612c53d0d2..0cb8d86ebce5 100644
>>>>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>>> @@ -461,12 +461,16 @@ syscrg: clock-controller@13020000 {
>>>>> <&gmac1_rgmii_rxin>,
>>>>> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>>>>> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>>>>> - <&tdm_ext>, <&mclk_ext>;
>>>>> + <&tdm_ext>, <&mclk_ext>,
>>>>> + <&pllclk JH7110_CLK_PLL0_OUT>,
>>>>> + <&pllclk JH7110_CLK_PLL1_OUT>,
>>>>> + <&pllclk JH7110_CLK_PLL2_OUT>;
>>>>> clock-names = "osc", "gmac1_rmii_refin",
>>>>> "gmac1_rgmii_rxin",
>>>>> "i2stx_bclk_ext", "i2stx_lrck_ext",
>>>>> "i2srx_bclk_ext", "i2srx_lrck_ext",
>>>>> - "tdm_ext", "mclk_ext";
>>>>> + "tdm_ext", "mclk_ext",
>>>>> + "pll0_out", "pll1_out", "pll2_out";
>>>>> #clock-cells = <1>;
>>>>> #reset-cells = <1>;
>>>>> };
>>>>> @@ -476,6 +480,13 @@ sys_syscon: syscon@13030000 {
>>>>> reg = <0x0 0x13030000 0x0 0x1000>;
>>>>> };
>>>>>
>>>>> + pllclk: pll-clock-controller {
>>>>
>>>> Does not look like you tested the DTS against bindings. Please run `make
>>>> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
>>>> for instructions). You should see here warnings of mixing non-MMIO nodes
>>>> in MMIO-bus.
>>>>
>>>
>>> Oh I cherry-pick the commit of syscon node and it also include the MMC node.
>>> I will remove the MMC node.
>>> I used dtbs_check and get the error 'should not be valid under {'type': 'object'}',
>>> If I move this node out of the 'soc' node, the dtbs_check will be pass.
>>> Is it OK to move the PLL node out of the 'soc' node? Thanks.
>>
>> Shall it be out side of soc? How it can then do anything with registers?
>> This does not look like correct representation of hardware.
>
> The error appears to be due to a lack of reg base about PLL node. PLL do something with register
> by 'sys_syscon' node and the syscon node is in the soc node.
Again: And how is this correct representation of hardware?
Best regards,
Krzysztof
prev parent reply other threads:[~2023-02-23 9:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 14:11 [PATCH v1 0/3] Add PLL clocks driver for StarFive JH7110 Xingyu Wu
2023-02-21 14:11 ` [PATCH v1 1/3] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-02-22 9:11 ` Krzysztof Kozlowski
2023-02-23 8:34 ` Xingyu Wu
2023-02-21 14:11 ` [PATCH v1 2/3] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-02-23 8:56 ` Krzysztof Kozlowski
2023-02-23 9:32 ` Xingyu Wu
2023-02-23 9:35 ` Krzysztof Kozlowski
2023-02-23 10:03 ` Xingyu Wu
2023-02-23 10:10 ` Krzysztof Kozlowski
2023-02-24 7:45 ` Xingyu Wu
2023-02-21 14:11 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add PLL clock node Xingyu Wu
2023-02-22 9:09 ` Krzysztof Kozlowski
2023-02-23 8:47 ` Xingyu Wu
2023-02-23 8:52 ` Krzysztof Kozlowski
2023-02-23 9:03 ` Xingyu Wu
2023-02-23 9:04 ` Krzysztof Kozlowski [this message]
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