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From: Rajendra Nayak <rnayak@codeaurora.org>
To: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Andy Gross <agross@kernel.org>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	DTML <devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Pradeep P V K <ppvk@codeaurora.org>,
	Veerabhadrarao Badiganti <vbadigan@codeaurora.org>,
	Subhash Jadavani <subhashj@codeaurora.org>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>
Subject: Re: [PATCH 13/21] mmc: sdhci-msm: Use OPP API to set clk/perf state
Date: Wed, 15 Apr 2020 22:13:19 +0530	[thread overview]
Message-ID: <3e5f8e78-7cd1-30fb-e005-78c1e7111794@codeaurora.org> (raw)
In-Reply-To: <CAPDyKFrOFOLCWHu8nE4i5t=d+Ei-kcJ15_42Ft3ROSUDe5jkpw@mail.gmail.com>



On 4/15/2020 7:22 PM, Ulf Hansson wrote:
> On Wed, 8 Apr 2020 at 15:48, Rajendra Nayak <rnayak@codeaurora.org> wrote:
>>
>> On some qualcomm SoCs we need to vote on a performance state of a power
>> domain depending on the clock rates. Hence move to using OPP api to set
>> the clock rate and performance state specified in the OPP table.
>> On platforms without an OPP table, dev_pm_opp_set_rate() is eqvivalent to
>> clk_set_rate()
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Ulf Hansson <ulf.hansson@linaro.org>
>> Cc: Pradeep P V K <ppvk@codeaurora.org>
>> Cc: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
>> Cc: Subhash Jadavani <subhashj@codeaurora.org>
>> Cc: linux-mmc@vger.kernel.org
> 
> This looks good to me!
> 
> However, are there any of the other patches in the series that
> $subject patch depends on - or can I apply this as a standalone mmc
> patch?

Hey Ulf, thanks for the review. I'll just need to respin these to make
sure I do not do a dev_pm_opp_of_remove_table() if dev_pm_opp_of_add_table()
isn;t successful as discussed with Viresh on another thread [1]

As for the dependencies, its only PATCH 01/21 in this series and that's
already been queued by Viresh [2]

[1] https://lkml.org/lkml/2020/4/15/18
[2] https://lkml.org/lkml/2020/4/14/98

> 
> Kind regards
> Uffe
> 
>> ---
>>   drivers/mmc/host/sdhci-msm.c | 20 ++++++++++++++++----
>>   1 file changed, 16 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>> index 09ff731..d82075a 100644
>> --- a/drivers/mmc/host/sdhci-msm.c
>> +++ b/drivers/mmc/host/sdhci-msm.c
>> @@ -10,6 +10,7 @@
>>   #include <linux/delay.h>
>>   #include <linux/mmc/mmc.h>
>>   #include <linux/pm_runtime.h>
>> +#include <linux/pm_opp.h>
>>   #include <linux/slab.h>
>>   #include <linux/iopoll.h>
>>   #include <linux/regulator/consumer.h>
>> @@ -242,6 +243,7 @@ struct sdhci_msm_host {
>>          struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
>>          struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
>>          unsigned long clk_rate;
>> +       struct opp_table *opp;
>>          struct mmc_host *mmc;
>>          bool use_14lpp_dll_reset;
>>          bool tuning_done;
>> @@ -332,7 +334,7 @@ static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
>>          int rc;
>>
>>          clock = msm_get_clock_rate_for_bus_mode(host, clock);
>> -       rc = clk_set_rate(core_clk, clock);
>> +       rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), clock);
>>          if (rc) {
>>                  pr_err("%s: Failed to set clock at rate %u at timing %d\n",
>>                         mmc_hostname(host->mmc), clock,
>> @@ -1963,7 +1965,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>>          msm_host->bulk_clks[0].clk = clk;
>>
>>          /* Vote for maximum clock rate for maximum performance */
>> -       ret = clk_set_rate(clk, INT_MAX);
>> +       ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
>>          if (ret)
>>                  dev_warn(&pdev->dev, "core clock boost failed\n");
>>
>> @@ -2087,6 +2089,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>>                  goto clk_disable;
>>          }
>>
>> +       msm_host->opp = dev_pm_opp_set_clkname(&pdev->dev, "core");
>> +       dev_pm_opp_of_add_table(&pdev->dev);
>> +
>>          pm_runtime_get_noresume(&pdev->dev);
>>          pm_runtime_set_active(&pdev->dev);
>>          pm_runtime_enable(&pdev->dev);
>> @@ -2109,10 +2114,12 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>>          return 0;
>>
>>   pm_runtime_disable:
>> +       dev_pm_opp_of_remove_table(&pdev->dev);
>>          pm_runtime_disable(&pdev->dev);
>>          pm_runtime_set_suspended(&pdev->dev);
>>          pm_runtime_put_noidle(&pdev->dev);
>>   clk_disable:
>> +       dev_pm_opp_set_rate(&pdev->dev, 0);
>>          clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
>>                                     msm_host->bulk_clks);
>>   bus_clk_disable:
>> @@ -2133,10 +2140,12 @@ static int sdhci_msm_remove(struct platform_device *pdev)
>>
>>          sdhci_remove_host(host, dead);
>>
>> +       dev_pm_opp_of_remove_table(&pdev->dev);
>>          pm_runtime_get_sync(&pdev->dev);
>>          pm_runtime_disable(&pdev->dev);
>>          pm_runtime_put_noidle(&pdev->dev);
>>
>> +       dev_pm_opp_set_rate(&pdev->dev, 0);
>>          clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
>>                                     msm_host->bulk_clks);
>>          if (!IS_ERR(msm_host->bus_clk))
>> @@ -2151,6 +2160,7 @@ static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
>>          struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>          struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
>>
>> +       dev_pm_opp_set_rate(dev, 0);
>>          clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
>>                                     msm_host->bulk_clks);
>>
>> @@ -2173,9 +2183,11 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
>>           * restore the SDR DLL settings when the clock is ungated.
>>           */
>>          if (msm_host->restore_dll_config && msm_host->clk_rate)
>> -               return sdhci_msm_restore_sdr_dll_config(host);
>> +               ret = sdhci_msm_restore_sdr_dll_config(host);
>>
>> -       return 0;
>> +       dev_pm_opp_set_rate(dev, msm_host->clk_rate);
>> +
>> +       return ret;
>>   }
>>
>>   static const struct dev_pm_ops sdhci_msm_pm_ops = {
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

  reply	other threads:[~2020-04-15 16:44 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-08 13:46 [PATCH 00/21] DVFS for IO devices on sdm845 and sc7180 Rajendra Nayak
2020-04-08 13:46 ` [PATCH 01/21] opp: Manage empty OPP tables with clk handle Rajendra Nayak
2020-04-09  7:57   ` Viresh Kumar
2020-04-13 10:34     ` Rajendra Nayak
2020-04-13 10:42       ` Viresh Kumar
2020-04-14  6:57   ` Viresh Kumar
2020-04-08 13:46 ` [PATCH 02/21] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-09 17:45   ` Matthias Kaehlcke
2020-04-10  8:36     ` Jun Nie
2020-04-13 14:22       ` Rajendra Nayak
2020-04-14  5:26         ` Jun Nie
2020-04-13 13:58     ` Rajendra Nayak
2020-04-10  6:56   ` Akash Asthana
2020-04-10 12:52     ` Akash Asthana
2020-04-13 14:13     ` Rajendra Nayak
2020-04-08 13:46 ` [PATCH 03/21] spi: spi-geni-qcom: " Rajendra Nayak
2020-04-09 18:20   ` Matthias Kaehlcke
2020-04-13 14:02     ` Rajendra Nayak
2020-04-08 13:46 ` [PATCH 04/21] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2020-04-08 13:46 ` [PATCH 05/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 06/21] scsi: ufs: Add support to manage multiple power domains in ufshcd-pltfrm Rajendra Nayak
2020-04-08 13:46 ` [PATCH 07/21] scsi: ufs: Add support for specifying OPP tables in DT Rajendra Nayak
2020-04-08 13:46 ` [PATCH 08/21] arm64: dts: sdm845: Add ufs opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 09/21] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-08 13:46 ` [PATCH 10/21] drm/msm: dsi: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 11/21] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 12/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 13/21] mmc: sdhci-msm: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-15 13:52   ` Ulf Hansson
2020-04-15 16:43     ` Rajendra Nayak [this message]
2020-04-16  3:39       ` Viresh Kumar
2020-04-16  8:21         ` Ulf Hansson
2020-04-16  8:23       ` Ulf Hansson
2020-04-08 13:46 ` [PATCH 14/21] arm64: dts: sdm845: Add sdhc opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 15/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 16/21] media: venus: core: Add support for opp tables/perf voting Rajendra Nayak
2020-04-08 13:46 ` [PATCH 17/21] arm64: dts: sdm845: Add OPP tables and power-domains for venus Rajendra Nayak
2020-04-08 13:46 ` [PATCH 18/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 19/21] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-08 13:46 ` [PATCH 20/21] arm64: dts: sdm845: Add qspi opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 21/21] arm64: dts: sc7180: " Rajendra Nayak

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