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AJvYcCXsPCIkrt54XeChokaHrKd1HzjA70RyVa0qGs0wcBvePDUrE95RgRbD6CoaDt/y3gIajuGzHbShO5Ld@vger.kernel.org X-Gm-Message-State: AOJu0YyukyGi8Xm5QKXEzrM7cQwlnvDeYpKHDEaVGcXWpmZmp4R919Rm r23vZBHtaSACQVSkGLz1gix6TDET8920ult10prTH4Qrt71tTuOoVu91L05ru+U= X-Google-Smtp-Source: AGHT+IGoE+jrhGDPxvzS+WZimT/uQDCBFmA0e0z1M8EFELzXgykeI+0Jev6cLL5gP+5Bp6fGDKWWLg== X-Received: by 2002:a17:907:3e12:b0:a9a:4fd3:c35f with SMTP id a640c23a62f3a-a9a69a63db8mr1206244266b.9.1729588077786; Tue, 22 Oct 2024 02:07:57 -0700 (PDT) Received: from [192.168.0.40] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a912d6267sm311979566b.32.2024.10.22.02.07.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Oct 2024 02:07:57 -0700 (PDT) Message-ID: <3ee7a1c9-2d6d-4fd5-982e-d86151e45662@linaro.org> Date: Tue, 22 Oct 2024 10:07:55 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] drm/msm/adreno: Add support for ACD To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org References: <20241021-gpu-acd-v2-0-9c25a62803bc@quicinc.com> <20241021-gpu-acd-v2-1-9c25a62803bc@quicinc.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20241021-gpu-acd-v2-1-9c25a62803bc@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 21/10/2024 12:53, Akhil P Oommen wrote: > ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce > the power consumption. In some chipsets, it is also a requirement to > support higher GPU frequencies. This patch adds support for GPU ACD by > sending necessary data to GMU and AOSS. The feature support for the > chipset is detected based on devicetree data. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 81 ++++++++++++++++++++++++++++------- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 + > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 ++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21 +++++++++ > 4 files changed, 124 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 37927bdd6fbe..09fb3f397dbb 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -1021,14 +1021,6 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) > > gmu->hung = false; > > - /* Notify AOSS about the ACD state (unimplemented for now => disable it) */ > - if (!IS_ERR(gmu->qmp)) { > - ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", > - 0 /* Hardcode ACD to be disabled for now */); > - if (ret) > - dev_err(gmu->dev, "failed to send GPU ACD state\n"); > - } > - > /* Turn on the resources */ > pm_runtime_get_sync(gmu->dev); > > @@ -1476,6 +1468,64 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) > return a6xx_gmu_rpmh_votes_init(gmu); > } > > +static int a6xx_gmu_acd_probe(struct a6xx_gmu *gmu) > +{ > + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); > + struct a6xx_hfi_acd_table *cmd = &gmu->acd_table; > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > + struct msm_gpu *gpu = &adreno_gpu->base; > + int ret, i, cmd_idx = 0; > + > + cmd->version = 1; > + cmd->stride = 1; > + cmd->enable_by_level = 0; > + > + /* Skip freq = 0 and parse acd-level for rest of the OPPs */ > + for (i = 1; i < gmu->nr_gpu_freqs; i++) { > + struct dev_pm_opp *opp; > + struct device_node *np; > + unsigned long freq; > + u32 val; > + > + freq = gmu->gpu_freqs[i]; > + opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, freq, true); > + np = dev_pm_opp_get_of_node(opp); > + > + ret = of_property_read_u32(np, "qcom,opp-acd-level", &val); > + of_node_put(np); > + dev_pm_opp_put(opp); > + if (ret == -EINVAL) > + continue; > + else if (ret) { > + DRM_DEV_ERROR(gmu->dev, "Unable to read acd level for freq %lu\n", freq); > + return ret; > + } > + > + cmd->enable_by_level |= BIT(i); > + cmd->data[cmd_idx++] = val; How do you know that cmd_idx is always < sizeof(cmd->data); ? > + } > + > + cmd->num_levels = cmd_idx; > + > + /* We are done here if ACD is not required for any of the OPPs */ > + if (!cmd->enable_by_level) > + return 0; > + > + /* Initialize qmp node to talk to AOSS */ > + gmu->qmp = qmp_get(gmu->dev); > + if (IS_ERR(gmu->qmp)) { > + cmd->enable_by_level = 0; > + return dev_err_probe(gmu->dev, PTR_ERR(gmu->qmp), "Failed to initialize qmp\n"); > + } > + > + /* Notify AOSS about the ACD state */ > + ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}", 1); > + if (ret) > + DRM_DEV_ERROR(gmu->dev, "failed to send GPU ACD state\n"); > + > + return 0; Shouldn't the ret from gmp_send() get propogated in the return of this function ? i.e. how can your probe be successful if the notification failed ? --- bod