Re: [PATCH v2 06/18] arm64: dts: qcom: sm6350: Add TLMM block node

[Maulik Shah <mkshah@codeaurora.org>]

Hi,

On 8/28/2021 6:48 PM, Konrad Dybcio wrote:
> Add TLMM pinctrl node to enable referencing the SoC pins in other nodes.
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> Changes since v1:
> - Fix the gpio ranges from 156 to 157
>
>   arch/arm64/boot/dts/qcom/sm6350.dtsi | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index d57c669ae0d6..03f7601457b4 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -406,6 +406,25 @@ pdc: interrupt-controller@b220000 {
>   			interrupt-controller;
>   		};
>   
> +		tlmm: pinctrl@f100000 {
> +			compatible = "qcom,sm6350-tlmm";
> +			reg = <0 0x0f100000 0 0x300000>;
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
you will not require other interrupts (209 to 216) for dual edge to work 
since you have below set in pinctrl-sm6350.c

.wakeirq_dual_edge_errata = true,

Thanks,
Maulik
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 157>;
> +		};
> +
>   		intc: interrupt-controller@17a00000 {
>   			compatible = "arm,gic-v3";
>   			#interrupt-cells = <3>;

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