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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id p5-20020a05600c358500b004053a6b8c41sm12225994wmq.12.2023.10.24.07.56.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Oct 2023 07:57:00 -0700 (PDT) Message-ID: <3f76f965-7c7b-109e-2ee0-3033e332e84b@linaro.org> Date: Tue, 24 Oct 2023 16:56:56 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v7 2/3] clocksource: Add JH7110 timer driver Content-Language: en-US To: Xingyu Wu , Thomas Gleixner , Emil Renner Berthing , Christophe JAILLET Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Walker Chen , Samin Guo , linux-kernel@vger.kernel.org, Conor Dooley References: <20231019053501.46899-1-xingyu.wu@starfivetech.com> <20231019053501.46899-3-xingyu.wu@starfivetech.com> From: Daniel Lezcano In-Reply-To: <20231019053501.46899-3-xingyu.wu@starfivetech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Xingyu, On 19/10/2023 07:35, Xingyu Wu wrote: > Add timer driver for the StarFive JH7110 SoC. As it is a new timer, please add a proper nice description explaining the timer hardware, thanks. > Signed-off-by: Xingyu Wu > --- > MAINTAINERS | 7 + > drivers/clocksource/Kconfig | 11 + > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-jh7110.c | 380 +++++++++++++++++++++++++++++ > 4 files changed, 399 insertions(+) > create mode 100644 drivers/clocksource/timer-jh7110.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 7a7bd8bd80e9..91c09b399131 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -20473,6 +20473,13 @@ S: Maintained > F: Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml > F: sound/soc/starfive/jh7110_tdm.c > > +STARFIVE JH7110 TIMER DRIVER > +M: Samin Guo > +M: Xingyu Wu > +S: Supported > +F: Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml > +F: drivers/clocksource/timer-jh7110.c > + > STARFIVE JH71X0 CLOCK DRIVERS > M: Emil Renner Berthing > M: Hal Feng > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 0ba0dc4ecf06..821abcc1e517 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -641,6 +641,17 @@ config RISCV_TIMER > is accessed via both the SBI and the rdcycle instruction. This is > required for all RISC-V systems. > > +config STARFIVE_JH7110_TIMER > + bool "Timer for the STARFIVE JH7110 SoC" > + depends on ARCH_STARFIVE || COMPILE_TEST You may want to use ARCH_STARFIVE only if the platform can make this timer optional. Otherwise, set the option from the platform Kconfig and put the bool "bla bla" if COMPILE_TEST > + select TIMER_OF > + select CLKSRC_MMIO > + default ARCH_STARFIVE no "default" > + help > + This enables the timer for StarFive JH7110 SoC. On RISC-V platform, > + the system has started RISCV_TIMER, but you can also use this timer > + which can provide four channels to do a lot more things on JH7110 SoC. > + > config CLINT_TIMER > bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST > depends on GENERIC_SCHED_CLOCK && RISCV > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile > index 368c3461dab8..b66ac05ec086 100644 > --- a/drivers/clocksource/Makefile > +++ b/drivers/clocksource/Makefile > @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o > obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o > obj-$(CONFIG_X86_NUMACHIP) += numachip.o > obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o > +obj-$(CONFIG_STARFIVE_JH7110_TIMER) += timer-jh7110.o > obj-$(CONFIG_CLINT_TIMER) += timer-clint.o > obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o > obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o > diff --git a/drivers/clocksource/timer-jh7110.c b/drivers/clocksource/timer-jh7110.c > new file mode 100644 > index 000000000000..71de29a3ec91 > --- /dev/null > +++ b/drivers/clocksource/timer-jh7110.c > @@ -0,0 +1,380 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Starfive JH7110 Timer driver > + * > + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. > + * > + * Author: > + * Xingyu Wu > + * Samin Guo > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Please double check the headers and remove the pointless ones. > +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */ > +#define JH7110_TIMER_CH_LEN 0x40 > +#define JH7110_TIMER_CH_BASE(x) ((x) * JH7110_TIMER_CH_LEN) > +#define JH7110_TIMER_CH_MAX 4 > + > +#define JH7110_CLOCK_SOURCE_RATING 200 > +#define JH7110_VALID_BITS 32 > +#define JH7110_DELAY_US 0 > +#define JH7110_TIMEOUT_US 10000 > +#define JH7110_CLOCKEVENT_RATING 300 > +#define JH7110_TIMER_MAX_TICKS 0xffffffff > +#define JH7110_TIMER_MIN_TICKS 0xf > +#define JH7110_TIMER_RELOAD_VALUE 0 > + > +#define JH7110_TIMER_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */ > +#define JH7110_TIMER_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */ > +#define JH7110_TIMER_LOAD 0x08 /* RW: load value to counter */ > +#define JH7110_TIMER_ENABLE 0x10 /* RW[0]: timer enable register */ > +#define JH7110_TIMER_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */ > +#define JH7110_TIMER_VALUE 0x18 /* RO: timer value register */ > +#define JH7110_TIMER_INT_CLR 0x20 /* RW: timer interrupt clear register */ > +#define JH7110_TIMER_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */ > + > +#define JH7110_TIMER_INT_CLR_ENA BIT(0) > +#define JH7110_TIMER_INT_CLR_AVA_MASK BIT(1) > + > +struct jh7110_clkevt { > + struct clock_event_device evt; > + struct clocksource cs; > + bool cs_is_valid; > + struct clk *clk; > + struct reset_control *rst; > + u32 rate; > + u32 reload_val; > + void __iomem *base; > + char name[sizeof("jh7110-timer.chX")]; > +}; > + > +struct jh7110_timer_priv { > + struct clk *pclk; > + struct reset_control *prst; > + struct jh7110_clkevt clkevt[JH7110_TIMER_CH_MAX]; Why do you need several clock events and clock sources ? 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