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Sun, 28 Jun 2026 23:43:43 -0700 (PDT) X-Received: by 2002:a17:902:d585:b0:2c9:afad:c5f2 with SMTP id d9443c01a7336-2c9afadc67fmr70320155ad.45.1782715423304; Sun, 28 Jun 2026 23:43:43 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c8c940b55asm50724605ad.76.2026.06.28.23.43.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Jun 2026 23:43:42 -0700 (PDT) Message-ID: <3f8d117c-2ced-480e-bec6-0bd38a60b7c0@oss.qualcomm.com> Date: Mon, 29 Jun 2026 12:13:36 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 13/13] arm64: dts: qcom: shikra: Add support for DISPCC/GPUCC nodes To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Brian Masney Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260604-shikra-dispcc-gpucc-v4-0-8204f1029311@oss.qualcomm.com> <20260604-shikra-dispcc-gpucc-v4-13-8204f1029311@oss.qualcomm.com> <77a5213d-6be7-4a86-81ad-3509a499ad12@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: <77a5213d-6be7-4a86-81ad-3509a499ad12@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA1NSBTYWx0ZWRfX7E0qL259ETWE iXegpHNzT2+jfbYnQhyyBc5+Ep4nF2L/wBfisrThLk391VO9sjm03043uYZM3aqM6+5andtf99t yoSPcf65YwsHwJY+ihnjW/mWv3jbTZ8= X-Authority-Analysis: v=2.4 cv=D+N37PRj c=1 sm=1 tr=0 ts=6a421420 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=LPMG5iTiuM7aS0oOI1MA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: -lTu2TV8RrBHCKSWGxNGL53HTcczNW8i X-Proofpoint-ORIG-GUID: -lTu2TV8RrBHCKSWGxNGL53HTcczNW8i X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA1NSBTYWx0ZWRfX3EwF6q71fYhF MkIalkHRJVHhgHwwhIt1TrAcndeAP42ZBk1EqrFXdfDRxtkoFoMVN/gK9rj4QwtQMryRXQ2MvoD yrKtvaSCghykd7VxIr9U/haOJw3OBIxtD/vbF7ivZRhVOGS9Hp+TVh8OLxgQIajTN8csG29SNAd 81IW6ukeybL48BLrxxgyYqb8cDrYLDh+Iq0WcdDigiHux5MDt1QOp8bdKer28aPw23FWnZPRsmA KIgav1V3tOviq0KdfWC5CXdz0j2kPuEY/jaSgINO2KvofEWX7oPvgtKizKsLaiqxR3ujEHerafE vDkeOA8HnyFB1qEwMux5gT0nJph3GFGLPFnQHEesraNfFebf3RSyLjw/yMrDZGraxu2nqBYDrVo R/OAQjH5D25Ci/y9PTzoxz/P55K4AFgCflGl1/p6ls5021Rr66s2eVqivXLELrbnk/UnjPk8g9q XtROf8sGCrTXnqo7EYQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290055 On 25-06-2026 02:14 pm, Konrad Dybcio wrote: > On 6/4/26 7:26 AM, Imran Shaik wrote: >> Add support for Display clock controller and GPU clock controller nodes >> on Qualcomm Shikra SoCs. >> >> Signed-off-by: Imran Shaik >> --- >> arch/arm64/boot/dts/qcom/shikra.dtsi | 41 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 41 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi >> index a4334d99c1f35ee851ca8266ec37d4a200a07ee5..1ccb0f1419aaa34d32f3c3eaabdb8727a497b501 100644 >> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi >> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi >> @@ -3,6 +3,8 @@ >> * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> */ >> >> +#include >> +#include >> #include >> #include >> #include >> @@ -640,6 +642,45 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, >> }; >> }; >> >> + gpucc: clock-controller@5990000 { >> + compatible = "qcom,shikra-gpucc"; >> + reg = <0x0 0x05990000 0x0 0x9000>; >> + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, >> + <&rpmcc RPM_SMD_XO_CLK_SRC>, >> + <&gcc GCC_GPU_GPLL0_CLK_SRC>, >> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; >> + power-domains = <&rpmpd RPMPD_VDDCX>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + dispcc: clock-controller@5f00000 { >> + compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; >> + reg = <0x0 0x05f00000 0x0 0x20000>; >> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, >> + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, >> + <&gcc GCC_DISP_GPLL0_CLK_SRC>, >> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <&sleep_clk>; >> + clock-names = "bi_tcxo", >> + "bi_tcxo_ao", > > Is the AO clock going to be any useful? Taniya recently dropped it > from some other submission after assessing it wasn't > The Agatti DISPCC driver is consuming the AO clock for the MDSS AHB clocks. As we are re-using the Agatti driver for Shikra, kept the AO clock as is. >> + "gcc_disp_gpll0_clk_src", >> + "gcc_disp_gpll0_div_clk_src", >> + "dsi0_phy_pll_out_byteclk", >> + "dsi0_phy_pll_out_dsiclk", >> + "dsi1_phy_pll_out_byteclk", >> + "dsi1_phy_pll_out_dsiclk", >> + "sleep_clk"; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; > > DISP_CC also needs to source power from somewhere! > The Shikra bindings aligns with the existing Agatti bindings, as it is a re-use. And the Shikra/Agatti DISPCC is on CX rail, and it will be always ON when APPS is active. Thanks, Imran