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From: Christian Bruel <christian.bruel@foss.st.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<mcoquelin.stm32@gmail.com>, <alexandre.torgue@foss.st.com>,
	<jingoohan1@gmail.com>, <p.zabel@pengutronix.de>,
	<johan+linaro@kernel.org>, <quic_schintav@quicinc.com>,
	<cassel@kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <fabrice.gasnier@foss.st.com>
Subject: Re: [PATCH v4 01/10] dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings
Date: Tue, 4 Feb 2025 12:07:06 +0100	[thread overview]
Message-ID: <3fa73c47-12af-46c3-8573-7d6800202e17@foss.st.com> (raw)
In-Reply-To: <20250202122527.ggy5ccz7o4umyhif@thinkpad>



On 2/2/25 13:25, Manivannan Sadhasivam wrote:
> On Tue, Jan 28, 2025 at 01:07:36PM +0100, Christian Bruel wrote:
> 
> [...]
> 
>> +    pcie@48400000 {
>> +        compatible = "st,stm32mp25-pcie-rc";
>> +        device_type = "pci";
>> +        reg = <0x48400000 0x400000>,
>> +              <0x10000000 0x10000>;
>> +        reg-names = "dbi", "config";
>> +        #interrupt-cells = <1>;
>> +        interrupt-map-mask = <0 0 0 7>;
>> +        interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
>> +                        <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
>> +                        <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
>> +                        <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
>> +        #address-cells = <3>;
>> +        #size-cells = <2>;
>> +        ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
>> +                 <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
>> +                 <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
>> +        dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
>> +        clocks = <&rcc CK_BUS_PCIE>;
>> +        resets = <&rcc PCIE_R>;
>> +        msi-parent = <&v2m0>;
>> +        wakeup-source;
> 
> Does this property really need to be present? If the WAKE# gpio is supported,
> isn't it implied that the RC is a wakeup source?
> 

the wakeup-source property is useless indeed with the wake_gpio, will 
remove,

thanks.

Christian

> - Mani
> 

  reply	other threads:[~2025-02-04 11:11 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-28 12:07 [PATCH v4 00/10] Add STM32MP25 PCIe drivers Christian Bruel
2025-01-28 12:07 ` [PATCH v4 01/10] dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings Christian Bruel
2025-01-29 15:44   ` Rob Herring
2025-02-02 12:25   ` Manivannan Sadhasivam
2025-02-04 11:07     ` Christian Bruel [this message]
2025-01-28 12:07 ` [PATCH v4 02/10] PCI: dwc: Add dw_pcie_wake_irq_handler helper Christian Bruel
2025-01-28 12:07 ` [PATCH v4 03/10] PCI: stm32: Add PCIe host support for STM32MP25 Christian Bruel
2025-02-02 13:06   ` Manivannan Sadhasivam
2025-02-04 16:23     ` Christian Bruel
2025-02-07 18:24       ` Manivannan Sadhasivam
2025-01-28 12:07 ` [PATCH v4 04/10] dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings Christian Bruel
2025-01-28 12:07 ` [PATCH v4 05/10] PCI: stm32: Add PCIe Endpoint support for STM32MP25 Christian Bruel
2025-01-28 12:07 ` [PATCH v4 06/10] MAINTAINERS: add entry for ST STM32MP25 PCIe drivers Christian Bruel
2025-01-28 12:07 ` [PATCH v4 07/10] arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi Christian Bruel
2025-01-28 12:07 ` [PATCH v4 08/10] arm64: dts: st: Add PCIe Rootcomplex mode on stm32mp251 Christian Bruel
2025-01-28 12:07 ` [PATCH v4 09/10] arm64: dts: st: Add PCIe Endpoint " Christian Bruel
2025-01-28 12:07 ` [PATCH v4 10/10] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board Christian Bruel

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