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Tue, 04 Feb 2025 12:10:50 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B0B314005A; Tue, 4 Feb 2025 12:09:21 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B78D92945D8; Tue, 4 Feb 2025 12:07:08 +0100 (CET) Received: from [10.129.178.212] (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 4 Feb 2025 12:07:07 +0100 Message-ID: <3fa73c47-12af-46c3-8573-7d6800202e17@foss.st.com> Date: Tue, 4 Feb 2025 12:07:06 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 01/10] dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings To: Manivannan Sadhasivam CC: , , , , , , , , , , , , , , , , , , References: <20250128120745.334377-1-christian.bruel@foss.st.com> <20250128120745.334377-2-christian.bruel@foss.st.com> <20250202122527.ggy5ccz7o4umyhif@thinkpad> From: Christian Bruel Content-Language: en-US In-Reply-To: <20250202122527.ggy5ccz7o4umyhif@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-04_05,2025-01-31_02,2024-11-22_01 On 2/2/25 13:25, Manivannan Sadhasivam wrote: > On Tue, Jan 28, 2025 at 01:07:36PM +0100, Christian Bruel wrote: > > [...] > >> + pcie@48400000 { >> + compatible = "st,stm32mp25-pcie-rc"; >> + device_type = "pci"; >> + reg = <0x48400000 0x400000>, >> + <0x10000000 0x10000>; >> + reg-names = "dbi", "config"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, >> + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, >> + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; >> + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; >> + clocks = <&rcc CK_BUS_PCIE>; >> + resets = <&rcc PCIE_R>; >> + msi-parent = <&v2m0>; >> + wakeup-source; > > Does this property really need to be present? If the WAKE# gpio is supported, > isn't it implied that the RC is a wakeup source? > the wakeup-source property is useless indeed with the wake_gpio, will remove, thanks. Christian > - Mani >