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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: FjjTQVS0L0d35qGxYGP0ZTq1hRaoiGNM X-Proofpoint-GUID: FjjTQVS0L0d35qGxYGP0ZTq1hRaoiGNM X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE2MDA1NSBTYWx0ZWRfXyiDS0yUSQHGU Loq+YY2SGtTVfegukCpwHfTXwMXMr0xrJU1wDZRyKpmMPHDq3oobP1rE/oWYQuCZMqneIxQ856P 1JDEkLS+ck2LhOy28+U6ivWtVf5mIgs= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE2MDA1NSBTYWx0ZWRfX11ndZhjrWdDu 3U1176qoUAapS6zFGJIonFEPnOnKWRyD4QgqkUPz98z406RZRchRXEaqW8oQ83/HSvgoy36rBZZ SJiHTR3tTTbw3wKaNNC77t3FszDlB8ltwkgcbqpt9OepICBQ3VKV7CRL7FYX7C+VcpzSUhU40Ra z6mtevmbXqIZtw/B3hPHe2n4dZHm6It/kJ/sJnNVZYlDI5jfoSio+hvYry9BxM3rPdkhrSzKmyT Bu0njpbpAwMmbmaTyJBw749QqkfVPSifP1Bpe+es2Kd9rOICubuy4IVPL+cCQJJ7ORm0tm0Vrmx eDHcU4esT14X+jhYEpQvR1ApSEbuDaQUBfn0FHTkK9IU35kcBOfh+ivT7lpKvOGmppy2t4iKqNg tJL6aYFQ5BhLwL90TeY6buh+Pp4F8gyNjBrO/4/Vp9texHancV8nASzHvZbQ5KZ7IKvd2zh3bYp KbcaJ1uxYtbHICI+aqQ== X-Authority-Analysis: v=2.4 cv=Se1i5fRu c=1 sm=1 tr=0 ts=6ad22ba0 cx=c_pps a=+D9SDfe9YZWTjADjLiQY5g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=RiPQFFr3Mvuh7BT_tTEA:9 a=QEXdDO2ut3YA:10 a=vmgOmaN-Xu0dpDh8OwbV:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-16_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 spamscore=0 malwarescore=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610160055 On 10/7/26 8:50 AM, Kathiravan Thirumoorthy wrote: > On IPQ9650, the bootloader configures and enables the APSS Zonda PLL > that provide the clocks for the A55 CPU cores and L3 interconnect. When > the APSS clock driver probes, it attempts to reconfigure the already > running PLLs. As part of the reconfiguration sequence, the PLL output is > disabled and the PLL is placed into standby before being re-enabled. > Since the CPUs are actively clocked from these PLLs, removing the clock > during this window causes the system to hang. > > Avoid reconfiguring PLLs that are already enabled and return early, > similar to clk_trion_pll_configure(). > > Signed-off-by: Kathiravan Thirumoorthy > --- > drivers/clk/qcom/clk-alpha-pll.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index 60173b076cc5..3641b2da92cd 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -2162,6 +2162,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); > void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, > const struct alpha_pll_config *config) > { > + /* Check if PLL is already enabled */ > + if (trion_pll_is_enabled(pll, regmap)) > + return; Please add a debug print to match the other similar calls with that: Reviewed-by: Konrad Dybcio Konrad