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Tue, 13 Jul 2021 09:56:00 +0000 Received: from [10.26.49.10] (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Jul 2021 09:55:56 +0000 Subject: Re: [PATCH] arm64: tegra: Enable SMMU support for PCIe on Tegra194 To: Vidya Sagar , , CC: , , , , , References: <20210713044414.25536-1-vidyas@nvidia.com> From: Jon Hunter Message-ID: <3fb8cabd-901b-d968-33da-cd163fe305dc@nvidia.com> Date: Tue, 13 Jul 2021 10:55:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210713044414.25536-1-vidyas@nvidia.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0cb124ed-6ed0-47f5-666e-08d945e46b53 X-MS-TrafficTypeDiagnostic: DM4PR12MB5359: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2582; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2021 09:56:00.3304 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cb124ed-6ed0-47f5-666e-08d945e46b53 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5359 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 13/07/2021 05:44, Vidya Sagar wrote: > As of commit c7289b1c8a4e ("arm64: tegra: Enable SMMU support on > Tegra194"), SMMU support is enabled system-wide on Tegra194. However, > there was a bit of overlap between the SMMU enablement and the PCIe > support addition, so the PCIe device tree nodes are missing the iommus > and interconnects properties. This in turn leads to SMMU faults for > these devices, since by default the ARM SMMU will fault. > > Add the iommus and interconnects properties to all the PCIe device > tree nodes to restore their functionality. > > Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194") > > Signed-off-by: Vidya Sagar > --- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 60 +++++++++++++++++++++--- > 1 file changed, 54 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > index 076d5efc4c3d..b55522aacfb0 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > @@ -1840,7 +1840,11 @@ > > interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, > <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; > - interconnect-names = "read", "write"; > + interconnect-names = "dma-mem", "dma-mem"; Thierry indicated that the convention we have been using is that only the entry is called 'dma-mem'. So could be good to update this to be consistent with the other interconnect-names entries. Otherwise ... Reviewed-by: Jon Hunter Cheers Jon -- nvpublic