From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A630200DB; Mon, 8 Jul 2024 14:09:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720447782; cv=none; b=N1euL8wNU3GvzoGnSG2KCNaH1cHIRUMoNLmt5j7xTHm4Hgn7xSY4W0W0T4meLknd2FSpE3tMaTIJuAK/+u2EDPkRoFcUz6QJZ1nWufjwsoWxo6CtY2lqeyW8LerZ74MoiViCL/qewL6bDkk96We77guC6mtkXvfzdvGUs5jgdjo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720447782; c=relaxed/simple; bh=CF0DPeRn5VszrUZffHovk/7+iBXFdC6spgWpYJy3pVU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=OiNQ/ggyG2Nq1a9BavYey5EvGn5NlCEzKgw6W/f+AQnhHSSjmjF2OJOqQotW8k3+GX6U/o/S+hOryGwXogiaX9I9dsAa1LTHm55U7gBw6zAvKEBntmRo5z74UqMLVEhWUrhvovH4dzQrSLM5WEHXivCNBO2qaq6LdBbLOUJPxGA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I7FiAjt+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I7FiAjt+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47AE8C116B1; Mon, 8 Jul 2024 14:09:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720447782; bh=CF0DPeRn5VszrUZffHovk/7+iBXFdC6spgWpYJy3pVU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=I7FiAjt+5agFJKcl0MnCIAu8UmE3zgEkkWzikd9B1U7dPWaAWJ3OMlReTXlK1nThf w5eJZxfz7MgEYo14ah66V3iJMJ17iX2f8LuLSkSV2yScACJPvILrzW0M/Qvw21mGa7 UO4CG8pldl9WzTJVmxAJyD5FiVqyCrdQqAo+eh/lSSLVaEego3Qt3EzDUB9jE53LVV xzdPkvH0WlAgv/3ci9jsYMUUyQAKg48OA/4hwCLeRA+sW+yNidOUUx9gmFbgWa5EUu d/Tbw1u3B1H5y/UlGCNSTkp3+yhOBqLrhJ05NFuw0vJOeECkdXdGkVn9PHOpWHgpi+ 2P0hoSJFekr5Q== Message-ID: <3fd67d12-4964-48eb-89cb-482b4a7e769d@kernel.org> Date: Mon, 8 Jul 2024 16:09:33 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/10] dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller To: Liu Ying , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, tglx@linutronix.de References: <20240705090932.1880496-1-victor.liu@nxp.com> <20240705090932.1880496-5-victor.liu@nxp.com> <31301581-a710-4e25-a079-e017686c52ec@nxp.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/07/2024 08:51, Liu Ying wrote: > On 07/07/2024, Krzysztof Kozlowski wrote: >> On 05/07/2024 11:09, Liu Ying wrote: >>> i.MX8qxp Display Controller has a built-in interrupt controller to support >>> Enable/Status/Preset/Clear interrupt bit. >>> >>> Signed-off-by: Liu Ying >>> --- >>> .../fsl,imx8qxp-dc-intc.yaml | 321 ++++++++++++++++++ >>> 1 file changed, 321 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml >>> new file mode 100644 >>> index 000000000000..3d0d11def505 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,imx8qxp-dc-intc.yaml >>> @@ -0,0 +1,321 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Freescale i.MX8qxp Display Controller interrupt controller >>> + >>> +description: | >>> + The Display Controller has a built-in interrupt controller with the following >>> + features for all relevant HW events: >>> + >>> + * Enable bit (mask) >>> + * Status bit (set by an HW event) >>> + * Preset bit (can be used by SW to set status) >>> + * Clear bit (used by SW to reset the status) >> >> 1. Why this is split from the main node? > > Maxime suggested to do so: > > " > But at least the CRTC and the interrupt controller should be split away, > or explained and detailed far better than "well it's just convenient". > " > > https://lore.kernel.org/lkml/2k3cc3yfwqlpquxrdmzmaafz55b3lnqomzxjsvtetfriliqj3k@tv6uh7dzc2ea/ > >> >> 2. Who can use this interrupt controller? Children of your display unit? > > Yes, only devices in the main display controller use it. > >> Then it is not really a separate device, is it? > > Er, per Maxime, it is a separate device. It's not for me, especially considering small register region used here. Srsly, with that claim, some I2C device like PMIC also has a separate interrupt controller, because interrupts are in separate few registers (e.g. status, mask and ack). Can any of the children interrupts be routed differently? Post entire, complete DTS for review. Best regards, Krzysztof