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[109.252.138.136]) by smtp.googlemail.com with ESMTPSA id a18sm4047834lfg.83.2022.02.02.07.45.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Feb 2022 07:45:10 -0800 (PST) Message-ID: <3feaa359-31bb-bb07-75d7-2a39c837a7a2@gmail.com> Date: Wed, 2 Feb 2022 18:45:09 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v18 2/4] dmaengine: tegra: Add tegra gpcdma driver Content-Language: en-US To: Akhil R , devicetree@vger.kernel.org, dmaengine@vger.kernel.org, jonathanh@nvidia.com, kyarlagadda@nvidia.com, ldewangan@nvidia.com, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, p.zabel@pengutronix.de, rgumasta@nvidia.com, robh+dt@kernel.org, thierry.reding@gmail.com, vkoul@kernel.org Cc: Pavan Kunapuli References: <1643729199-19161-1-git-send-email-akhilrajeev@nvidia.com> <1643729199-19161-3-git-send-email-akhilrajeev@nvidia.com> From: Dmitry Osipenko In-Reply-To: <1643729199-19161-3-git-send-email-akhilrajeev@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org .... > +static int tegra_dma_pause(struct tegra_dma_channel *tdc) > +{ > + int ret; > + u32 val; > + > + val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); > + val |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE; > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); > + > + /* Wait until busy bit is de-asserted */ > + ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + > + tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, > + val, > + !(val & TEGRA_GPCDMA_STATUS_BUSY), > + TEGRA_GPCDMA_BURST_COMPLETE_TIME, > + TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); > + > + return ret; > +} > + > +static int tegra_dma_device_pause(struct dma_chan *dc) > +{ > + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); > + unsigned long flags; > + int ret = 0; > + > + if (!tdc->tdma->chip_data->hw_support_pause) > + return -ENOSYS; > + > + spin_lock_irqsave(&tdc->vc.lock, flags); > + ret = tegra_dma_pause(tdc); > + if (ret) > + dev_err(tdc2dev(tdc), "DMA pause timed out\n"); Why error message shouldn't be printed by tegra_dma_terminate_all()? The error message should be placed inside of tegra_dma_pause(). ... > +static int tegra_dma_stop_client(struct tegra_dma_channel *tdc) > +{ > + int ret; > + unsigned long status; > + u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); > + > + /* > + * Change the client associated with the DMA channel > + * to stop DMA engine from starting any more bursts for > + * the given client and wait for in flight bursts to complete > + */ > + csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK); > + csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED; > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); > + > + /* Wait for in flight data transfer to finish */ > + udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME); > + > + /* If TX/RX path is still active wait till it becomes > + * inactive > + */ > + > + ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + > + tdc->chan_base_offset + > + TEGRA_GPCDMA_CHAN_STATUS, > + status, > + !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX | > + TEGRA_GPCDMA_STATUS_CHANNEL_RX)), > + 5, > + TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); > + if (ret) { > + dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n"); > + tegra_dma_dump_chan_regs(tdc); > + } > + > + return ret; > +} > + > +static int tegra_dma_terminate_all(struct dma_chan *dc) > +{ > + struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); > + unsigned long flags; > + LIST_HEAD(head); > + int err; > + > + spin_lock_irqsave(&tdc->vc.lock, flags); > + > + if (tdc->dma_desc) { > + err = tdc->tdma->chip_data->hw_support_pause ? > + tegra_dma_pause(tdc) : > + tegra_dma_stop_client(tdc); The canonical coding style is: if (tdc->tdma->chip_data->hw_support_pause) err = tegra_dma_pause(tdc); else err = tegra_dma_stop_client(tdc); But why do you need to pause at all here and can't use tegra_dma_stop_client() even if pause is supported?