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Mon, 07 Sep 2026 04:17:58 -0700 (PDT) Message-ID: <4056ce28-cbf6-46cc-8bcf-a3db35410275@gmail.com> Date: Mon, 7 Sep 2026 13:17:55 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 05/17] iio: adc: Add AD7768 and AD7768-4 core support To: Andy Shevchenko , Janani Sunil Cc: =?UTF-8?Q?Nuno_S=C3=A1?= , Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle , Randy Dunlap , linux@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= References: <20260904-ad7768-driver-v6-0-e4378f946bfb@analog.com> <20260904-ad7768-driver-v6-5-e4378f946bfb@analog.com> Content-Language: en-US From: Janani Sunil In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/6/26 10:34, Andy Shevchenko wrote: > On Fri, Sep 04, 2026 at 04:14:57PM +0200, Janani Sunil wrote: >> Add core support for the AD7768 and AD7768-4 simultaneous sampling ADCs. >> Configure supplies, clock and reset, use a custom regmap bus for the SPI >> protocol, and parse the enabled channels and input buffer settings from >> devicetree. >> >> Connect the converter to an IIO backend for buffered capture with CRC, >> provide a fixed safe wideband sampling configuration and add runtime >> power management. > ... > >> + /* >> + * DCLK(min) is ODR * channels per DOUTx * 32. With fast mode >> + * (fMOD = MCLK / 4) and x64 decimation, this gives: >> + * MCLK / DCLK = 8 * data lines / channels. >> + */ >> + dclk_div = 8 * st->datalines / st->chip_info->num_channels; >> + dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV(dclk_div); > So, this one is (4 - ffs(dclk_div)). If num_channels == 1, this will always give 0. > If num_channels == 2, this might give 0, 8, ... Since ffs(0) implementation is defined > to return 0, this will return... 0! So, tell me how this code may return > anything than 0? The st->chip_info->num_channels is fixed at either 8 (AD7768) or 4 (AD7768-4) and not the number of channels described in the firmware. The supported dataline configurations produce dclk_div of 1, 2 or 8 and register values of 3, 2 or 0. However, I agree that using the ffs() obscures this mapping, so I will replace it with an explicit switch over the supported divider values. Regards, Jan