From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AF983F076A; Tue, 20 Jan 2026 10:43:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768905836; cv=none; b=K7MmRib898TSyGnGl8U5GJwXvMkDWrrbBcquu2oKxi14Zl4pKurZD7ximpWK0Z3F1XDDZPryg6zEDPpGhjlF/yIedo8uK0XVrFICJ2Q4xsGGee/0KrBPzaNYkfoor4BEaWA4i/SQHnlprZy7YxRSllpA1nXRhhotvXxzYwCk7qA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768905836; c=relaxed/simple; bh=O2FhviPnC5jz5ZsBAwO6tzGpttxJxSsq9OxCi424fEk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tFN/GqgsNJWDLstrkfDlhS8L3F/L1D6aI0Fa77YDuB/KrhvGuN6FjFN/zuRuOQ0ZyBv0M0AGT4n2qTlUVjAnVyqreT2tCfwTsttlwqm7BPE53Ns9ZQaOmKCWQpqVm79jG+gLPKnxTN575fSqj/yYhwOFM6uLGGcZq8x+rPsx3UY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=lxZMgDnA; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="lxZMgDnA" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To; bh=O2FhviPnC5jz5ZsBAwO6tzGpttxJxSsq9OxCi424fEk=; b=lxZMgDnA7WGotJ0c12IMFqkU7a rwtU+DoqMrphu1iorjPcGFxsr1p0/WtuZXWjU9WIWLzaIIDwgRAjmFpdOQr72wpzlEwBRKSxY1jUA zpKgaOK1KezXk/bc0zdRwF7YZmrCBgt3CfDv/jmR5HEsJVlsQXdkH02mqs4lak3nNBx/pU6YyXQdL W1t7Y+39lfIc1Tmxok2lYKPNC1R9UPgCAimMDW9NEIo2H/i1hxwJBdr+RUtsyVUVsJwuwCeaPrHVM 9QUlDYrhBFOrjOYNZHJM4IMdbqwJz7kzu0vi+vdAwxQXChIf+0jbUeOWnPBcIZNAi5VLurg7Qy9Tg Oqh96xGg==; Received: from [192.76.154.238] (helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vi9D4-003N5V-46; Tue, 20 Jan 2026 11:43:42 +0100 From: Heiko Stuebner To: dmitry.baryshkov@oss.qualcomm.com, Andy Yan Cc: krzk+dt@kernel.org, conor+dt@kernel.org, cristian.ciocaltea@collabora.com, Laurent.pinchart@ideasonboard.com, mripard@kernel.org, hjc@rock-chips.com, robh@kernel.org, sebastian.reichel@collabora.com, tzimmermann@suse.de, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Andy Yan Subject: Re: [PATCH 2/5] drm/bridge: synopsys: dw-dp: Set pixel mode by platform data Date: Tue, 20 Jan 2026 11:43:41 +0100 Message-ID: <4083071.q0ZmV6gNhb@phil> In-Reply-To: <20260109080054.228671-3-andyshrk@163.com> References: <20260109080054.228671-1-andyshrk@163.com> <20260109080054.228671-3-andyshrk@163.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Freitag, 9. Januar 2026, 09:00:45 Mitteleurop=C3=A4ische Normalzeit schr= ieb Andy Yan: > From: Andy Yan >=20 > The DW DisplayPort hardware block can be configured to work in single, > dual,quad pixel mode on differnt platforms, so make the pixel mode set > by plat_data to support the upcoming rk3576 variant. >=20 > Signed-off-by: Andy Yan While Dmitry helped a lot with looking at bridge drivers recently, I think your recipient list does miss a number of other people listed as bridge reviewers/maintainers. $ scripts/get_maintainer.pl drivers/gpu/drm/bridge Andrzej Hajda (maintainer:DRM DRIVERS FOR BRIDGE = CHIPS) Neil Armstrong (maintainer:DRM DRIVERS FOR BRID= GE CHIPS) Robert Foss (maintainer:DRM DRIVERS FOR BRIDGE CHIPS) Laurent Pinchart (reviewer:DRM DRIVERS = =46OR BRIDGE CHIPS) Jonas Karlman (reviewer:DRM DRIVERS FOR BRIDGE CHIPS) Jernej Skrabec (reviewer:DRM DRIVERS FOR BRIDGE = CHIPS) As you'll need to do a v2 for the binding, please add the missing people to the recipients. =46or the change itself, can you improve the commit message a bit. I assume the Single/Dual/Quad-Pixel config is a real hardware-feature that is set when the IP is integrated into the soc? Or this a runtime setting and a soc can support multiple output variants? Thanks Heiko