From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FA6F1E2875; Fri, 2 Aug 2024 14:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722609255; cv=none; b=rbEEC+tHl0YCKZth/2mpNslPhao3yZX/fq6wum1KKwl5Ki4SieA/KMlJwWPUsYuSRCfvVFcPdAIlP9CjhtZysoijljxxpH4fXufPUilVYvK/fhKCd15/He2d5Umi8c0XtMezD5peI2aRUd1znb/5rt0xn1G7d9O96EEZhQ13JIQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722609255; c=relaxed/simple; bh=kT1NudS6A1VBu00pH0wix5fkzSs86n7Vt9obyt3Xj/g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ohcZxINWL4omT/QZh0RAukrG7b51n3x9GlEW3ncU47MYu8hhJKRindDhQfod31aNcgDQpVSWrK0MRZRBO6LdJxvfLZ4ogmCDobaU3Fn1VyvsM8LMY6++P7uByOxftAv6+vxtjiNRuEUS6IaAm9QuUsPpmKvjHHpSj9mujCaQPt4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i53875a76.versanet.de ([83.135.90.118] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sZtM9-0002uP-Ce; Fri, 02 Aug 2024 16:34:09 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: linux-kernel@vger.kernel.org, Detlev Casanova Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Elaine Zhang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Sugar Zhang , Detlev Casanova Subject: Re: [PATCH 2/3] clk: rockchip: Add dt-binding header for rk3576 Date: Fri, 02 Aug 2024 16:34:07 +0200 Message-ID: <4084310.iTQEcLzFEP@diego> In-Reply-To: <20240802141816.288337-3-detlev.casanova@collabora.com> References: <20240802141816.288337-1-detlev.casanova@collabora.com> <20240802141816.288337-3-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Hi Detlev, Am Freitag, 2. August 2024, 16:12:49 CEST schrieb Detlev Casanova: > From: Elaine Zhang > > Add the dt-bindings header for the rk3576, that gets shared between > the clock controller and the clock references in the dts. > > Signed-off-by: Elaine Zhang > Signed-off-by: Sugar Zhang > Signed-off-by: Detlev Casanova > --- > .../dt-bindings/clock/rockchip,rk3576-cru.h | 1149 +++++++++++++++++ > 1 file changed, 1149 insertions(+) > create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h > > diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h > new file mode 100644 > index 0000000000000..19d25f082dc57 > --- /dev/null > +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h > @@ -0,0 +1,1149 @@ > +#define CLK_NR_CLKS (ACLK_KLAD + 1) this needs to go please. Take a look at how Sebastian got rid of needed that max-constant for rk3588. [...] > +#define SRST_H_VEPU1 1267 > +#define SRST_A_VEPU1 1268 > +#define SRST_VEPU1_CORE 1269 > + > +/********Name=PHPPHYSOFTRST_CON00,Offset=0x8A00********/ > +#define SRST_P_PHPPHY_CRU 131073 > +#define SRST_P_APB2ASB_SLV_CHIP_TOP 131075 > +#define SRST_P_PCIE2_COMBOPHY0 131077 > +#define SRST_P_PCIE2_COMBOPHY0_GRF 131078 > +#define SRST_P_PCIE2_COMBOPHY1 131079 > +#define SRST_P_PCIE2_COMBOPHY1_GRF 131080 this seems to lump together different components and with that creates these gaps. I.e. I really don't think the phpphy in these registers is part of the core CRU. That huge memory length of 0x5c000 in your dt-binding is also a good indicator that this needs to have more separation and not span multiple devices. > +/********Name=PHPPHYSOFTRST_CON01,Offset=0x8A04********/ > +#define SRST_PCIE0_PIPE_PHY 131093 > +#define SRST_PCIE1_PIPE_PHY 131096 > + > +/********Name=SECURENSSOFTRST_CON00,Offset=0x10A00********/ > +#define SRST_H_CRYPTO_NS 262147 > +#define SRST_H_TRNG_NS 262148 > +#define SRST_P_OTPC_NS 262152 > +#define SRST_OTPC_NS 262153 > + > +/********Name=PMU1SOFTRST_CON00,Offset=0x20A00********/ > +#define SRST_P_HDPTX_GRF 524288 same here, that is also most likely not part of the CRU but a different block. Other socs already implement separate clock controllers for different parts, so please take a look there. Thanks Heiko