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Sun, 13 Apr 2025 11:29:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1744536543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qLigHGDaIeu/1Png7nmdn+cp2yXJhXD50jHy7YJID8c=; b=VNCSjzTk21Eve7Z+hAqaCoAoIaDO686a1/uXqp2xVsziv26bF5vn6E9rsnU2/ugYcJjrI5 syuFZWiDwaseaXZRo+WyhhWeFDtw9ycr6zfxHpodzkx0WrXEXc/qDIbQzREeCkesOlRbnm POuIINCHvixCQ/vclA/kbYEs21KEMXeRsujd0LTzVgdVdpkaEdlcH4kN11LvJAVweYnjf0 ZSDEZ5f9crvnuMyDK1gttT/D7EWeBQG5wQR2ONBpZBVDmVJvMlqgDkct1GSImhLkHxb8Og M+cRGpS4cFMkZcyLMAzUiqzALHwN52cNWOQ3kgblqZEjA5t0mqa5Ao5+hIZPtg== Message-ID: <40c400ab-8770-4595-9a4c-004e6157c348@mailbox.org> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1744536541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qLigHGDaIeu/1Png7nmdn+cp2yXJhXD50jHy7YJID8c=; b=Z5hHSyYGUjCJ8sxEk2uc5ghic5sz5e161r4Uzv5vy9eHgrABVAWnuMIWd7jNQ3IY0PR+mj NElEyXHt9jEOUHCmcuhUVQLyFDvJzGDofkOKs9+PJI4bRM6edNgnr/h0yyBp9U/i7gZFsz 7eA8jBRPtuh67u5wRTV7Abl1BcYvr/XEEpAgI93xMhX7YOTHUoVb8qgHEXLvFRLr4zIhkQ O0jiQB0yb+VxZ+kwBbzj2zomPxkwut6ybYHgahwx5wkXZSzAAUUg7A/CW/fSsDQT1xxI+F 8Tj0gGHmpTeZtVCKjZLdzmjT4H0+Huhc9mc0+Q/YM2SKH7174AnR5sg/I3yT/Q== Date: Sun, 13 Apr 2025 11:28:54 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock To: Rob Herring , Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, =?UTF-8?Q?Niklas_S=C3=B6derlund?= , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> <20250406144822.21784-2-marek.vasut+renesas@mailbox.org> <20250410204845.GA1027003-robh@kernel.org> Content-Language: en-US From: Marek Vasut In-Reply-To: <20250410204845.GA1027003-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-MBO-RS-ID: 56af0dbc93e5c7e09ea X-MBO-RS-META: pc3z5wauiworu1bkpr5dqhfdbznjkp6g X-Rspamd-Queue-Id: 4Zb4qg1q66z9t87 On 4/10/25 10:48 PM, Rob Herring wrote: > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: >> Document 'aux' clock which are used to supply the PCIe bus. This >> is useful in case of a hardware setup, where the PCIe controller >> input clock and the PCIe bus clock are supplied from the same >> clock synthesiser, but from different differential clock outputs: >> >> ____________ _____________ >> | R-Car PCIe | | PCIe device | >> | | | | >> | PCIe RX<|==================|>PCIe TX | >> | PCIe TX<|==================|>PCIe RX | >> | | | | >> | PCIe CLK<|======.. ..======|>PCIe CLK | >> '------------' || || '-------------' >> || || >> ____________ || || >> | 9FGV0441 | || || >> | | || || >> | CLK DIF0<|======'' || >> | CLK DIF1<|=========='' >> | CLK DIF2<| >> | CLK DIF3<| >> '------------' >> >> The clock are named 'aux' because those are one of the clock listed in >> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which >> fit closest to the PCIe bus clock. According to that binding document, >> the 'aux' clock describe clock which supply the PMC domain, which is >> likely PCIe Mezzanine Card domain. > > Pretty sure that PMC is "power management controller" given it talks > about low power states. > > >> >> Tested-by: Niklas Söderlund >> Signed-off-by: Marek Vasut >> --- >> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml >> instead and add 'bus' clock outright ? > > Based on the diagram, this has nothing to do with the specific > controller. It should also probably a root port property, not host > bridge. How would you suggest I describe the clock which supply the PCIe bus clock lane (CLK DIF1 in the diagram) , which have to be enabled together with clock which supply the PCIe controller input clock lane (CLK DIF0) ?