Re: [PATCH RFC v2 2/6] drm/msm/adreno: rename llc_mmio to cx_misc_mmio

[Akhil P Oommen <akhilpo@oss.qualcomm.com>]

On 4/3/2026 4:39 AM, Alexander Koskovich wrote:
> This region is used for more than just LLCC, it also provides access to
> software fuse values (raytracing, etc).
> 
> Rename relevant symbols from _llc to _cx_misc for use in a follow up
> change that decouples this from LLCC.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

-Akhil

> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c |  8 ++++----
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++--------
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +++++++-------
>  drivers/gpu/drm/msm/adreno/a8xx_gpu.c |  2 +-
>  4 files changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 916c5d99c4d1..23e5b3a22ea5 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -947,7 +947,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
>  
>  	/* Turn on TCM (Tightly Coupled Memory) retention */
>  	if (adreno_is_a7xx(adreno_gpu))
> -		a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
> +		a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
>  	else if (!adreno_is_a8xx(adreno_gpu))
>  		gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
>  
> @@ -1215,7 +1215,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
>  		if (!qcom_scm_is_available()) {
>  			dev_warn_once(gpu->dev->dev,
>  				"SCM is not available, poking fuse register\n");
> -			a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
> +			a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
>  				A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
>  				A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
>  				A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
> @@ -1236,7 +1236,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
>  		 * firmware, find out whether that's the case. The scm call
>  		 * above sets the fuse register.
>  		 */
> -		fuse_val = a6xx_llc_read(a6xx_gpu,
> +		fuse_val = a6xx_cx_misc_read(a6xx_gpu,
>  					 REG_A7XX_CX_MISC_SW_FUSE_VALUE);
>  		adreno_gpu->has_ray_tracing =
>  			!!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
> @@ -1299,7 +1299,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
>  
>  	/* Check to see if we are doing a cold or warm boot */
>  	if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
> -		status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
> +		status = a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
>  			GMU_WARM_BOOT : GMU_COLD_BOOT;
>  	} else if (gmu->legacy) {
>  		status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index e1eae6cb1e40..9847f83b92af 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
>  	struct msm_gpu *gpu = &adreno_gpu->base;
>  	u32 cntl1_regval = 0;
>  
> -	if (IS_ERR(a6xx_gpu->llc_mmio))
> +	if (IS_ERR(a6xx_gpu->cx_misc_mmio))
>  		return;
>  
>  	if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
> @@ -2078,14 +2078,14 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
>  	 * pagetables
>  	 */
>  	if (!a6xx_gpu->have_mmu500) {
> -		a6xx_llc_write(a6xx_gpu,
> +		a6xx_cx_misc_write(a6xx_gpu,
>  			REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
>  
>  		/*
>  		 * Program cacheability overrides to not allocate cache
>  		 * lines on a write miss
>  		 */
> -		a6xx_llc_rmw(a6xx_gpu,
> +		a6xx_cx_misc_rmw(a6xx_gpu,
>  			REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
>  		return;
>  	}
> @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
>  	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
>  	struct msm_gpu *gpu = &adreno_gpu->base;
>  
> -	if (IS_ERR(a6xx_gpu->llc_mmio))
> +	if (IS_ERR(a6xx_gpu->cx_misc_mmio))
>  		return;
>  
>  	if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
> @@ -2151,15 +2151,15 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
>  	of_node_put(phandle);
>  
>  	if (is_a7xx || !a6xx_gpu->have_mmu500)
> -		a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem");
> +		a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem");
>  	else
> -		a6xx_gpu->llc_mmio = NULL;
> +		a6xx_gpu->cx_misc_mmio = NULL;
>  
>  	a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
>  	a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
>  
>  	if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
> -		a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> +		a6xx_gpu->cx_misc_mmio = ERR_PTR(-EINVAL);
>  }
>  
>  #define GBIF_CLIENT_HALT_MASK		BIT(0)
> @@ -2560,7 +2560,7 @@ static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,
>  		return ret;
>  
>  	if (info->quirks & ADRENO_QUIRK_SOFTFUSE) {
> -		*speedbin = a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
> +		*speedbin = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
>  		*speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin);
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index eb431e5e00b1..648608c1c98e 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -102,7 +102,7 @@ struct a6xx_gpu {
>  
>  	bool has_whereami;
>  
> -	void __iomem *llc_mmio;
> +	void __iomem *cx_misc_mmio;
>  	void *llc_slice;
>  	void *htw_llc_slice;
>  	bool have_mmu500;
> @@ -240,19 +240,19 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
>  	return true;
>  }
>  
> -static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
> +static inline void a6xx_cx_misc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
>  {
> -	return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
> +	return msm_rmw(a6xx_gpu->cx_misc_mmio + (reg << 2), mask, or);
>  }
>  
> -static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
> +static inline u32 a6xx_cx_misc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
>  {
> -	return readl(a6xx_gpu->llc_mmio + (reg << 2));
> +	return readl(a6xx_gpu->cx_misc_mmio + (reg << 2));
>  }
>  
> -static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
> +static inline void a6xx_cx_misc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
>  {
> -	writel(value, a6xx_gpu->llc_mmio + (reg << 2));
> +	writel(value, a6xx_gpu->cx_misc_mmio + (reg << 2));
>  }
>  
>  #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> index 9e6f2ed69247..8b4b022d9a6b 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> @@ -103,7 +103,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu)
>  		return;
>  	}
>  
> -	slice_mask &= a6xx_llc_read(a6xx_gpu,
> +	slice_mask &= a6xx_cx_misc_read(a6xx_gpu,
>  			REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL);
>  
>  	a6xx_gpu->slice_mask = slice_mask;
>