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[81.167.86.93]) by smtp.gmail.com with ESMTPSA id c23-20020a056512325700b0048374164e22sm1159225lfr.193.2022.07.22.10.36.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Jul 2022 10:36:03 -0700 (PDT) Message-ID: <4133c99a-b6a1-6a17-0ad8-f3bf6f8ab176@linaro.org> Date: Fri, 22 Jul 2022 19:36:01 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v4 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Content-Language: en-US To: Bjorn Helgaas Cc: wangseok.lee@samsung.com, "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" , Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim References: <20220721205819.GA1753070@bhelgaas> From: Krzysztof Kozlowski In-Reply-To: <20220721205819.GA1753070@bhelgaas> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 21/07/2022 22:58, Bjorn Helgaas wrote: > On Thu, Jul 21, 2022 at 11:04:00AM +0200, Krzysztof Kozlowski wrote: >> On 20/07/2022 08:01, Wangseok Lee wrote: >>> Add support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis >>> Communications. This is based on arm64 and support GEN4 & 2lane. This >>> PCIe controller is based on DesignWare Hardware core and uses DesignWare >>> core functions to implement the driver. "pcie-artpec6. c" supports artpec6 >>> and artpec7 H/W. artpec8 can not be expanded because H/W configuration is >>> completely different from artpec6/7. PHY and sub controller are different. >>> >>> Signed-off-by: Wangseok Lee >>> Signed-off-by: Jaeho Cho >>> --- >>> v3->v4 : >>> -Remove unnecessary enum type >>> -Fix indentation >>> >> >> Thanks for the changes. This starts to look good, however I am not going >> to ack it. This is also not a strong NAK, as I would respect Bjorn and >> other maintainers decision. >> >> I don't like the approach of creating only Artpec-8 specific driver. >> Samsung heavily reuses its block in all Exynos devices. Now it re-uses >> them for other designs as well. Therefore, even if merging with existing >> Exynos PCIe driver is not feasible (we had such discussions), I expect >> this to cover all Samsung Foundry PCIe devices. From all current designs >> up to future licensed blocks, including some new Samsung Exynos SoC. Or >> at least be ready for it. > > I would certainly prefer fewer drivers but I don't know enough about > the underlying IP and the places it's integrated to to know what's > practical. The only way I could figure that out would be by manually > comparing the drivers for similarity. I assume/expect all driver > authors are doing that. Merging with existing Exynos PCIe driver (and phy) might be indeed tricky, as existing one does not support that much as here. However I really expect that all current designs from Samsung - Exynos SoC, Artpec and for other customers - have very similar PCIe thus this should be a generic, new generation Samsung PCIe driver. If designed that way, also the naming should be back Samsung specific, no Axis/Artpec. Best regards, Krzysztof