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Wed, 10 Jul 2024 07:18:45 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46A7IilF015641 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jul 2024 07:18:44 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 10 Jul 2024 00:18:38 -0700 Message-ID: <417ff30e-87d9-4816-addc-943f96ec64ac@quicinc.com> Date: Wed, 10 Jul 2024 15:18:36 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC To: Bjorn Helgaas CC: Manivannan Sadhasivam , "Lorenzo Pieralisi" , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , , , , , References: <20240709162621.GA175973@bhelgaas> From: Tengfei Fan In-Reply-To: <20240709162621.GA175973@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FMFiu0mJ3ebQ_-I4SHSCVkL4oHTerKB_ X-Proofpoint-ORIG-GUID: FMFiu0mJ3ebQ_-I4SHSCVkL4oHTerKB_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-10_03,2024-07-09_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 adultscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407100051 On 7/10/2024 12:26 AM, Bjorn Helgaas wrote: > On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote: >> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, >> so add support for it by passing the mapping format and the number of >> read/write channels count. >> >> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate >> config struct is introduced for the sake of enabling HDMA conditionally. > > This patch doesn't add a new config struct. Thank you for pointing out this. I will remove this commit message in the next version patch series. > >> It should be noted that for the eDMA support (predecessor of HDMA), there >> are no mapping format and channels count specified. That is because eDMA >> supports auto detection of both parameters, whereas HDMA doesn't. >> >> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p >> platform use non-SCMI resource. In the future, the SA8775p platform will >> move to use SCMI resources and it will have new sa8775p-related device >> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device >> match table. > > This series doesn't add the new SCMI stuff you mention. It sounds > like this should be deferred and added when you actually move to using > SCMI resources. This patch shouldn't be deferred. This patch is used to support QSC9100. QCS9100 uses non-SCMI resources, so there is nothing related to SCMI in this patch. Only SA8775p will move to use SCMI resources in the future. > >> Signed-off-by: Tengfei Fan >> --- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> index 236229f66c80..e2775f4ca7ee 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { >> }; >> >> static const struct of_device_id qcom_pcie_ep_match[] = { >> + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, >> { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, >> { .compatible = "qcom,sdx55-pcie-ep", }, >> { .compatible = "qcom,sm8450-pcie-ep", }, >> >> -- >> 2.25.1 >> -- Thx and BRs, Tengfei Fan