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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id n16-20020a05640204d000b0042062f9f0e1sm4154445edw.15.2022.04.25.00.52.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Apr 2022 00:52:41 -0700 (PDT) Message-ID: <418c5f0c-5279-41f5-3705-345ec9a97ea2@linaro.org> Date: Mon, 25 Apr 2022 09:52:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH V3 12/17] dt-binding: mt8192: Add infra_ao reset bit Content-Language: en-US To: Rex-BC Chen , "mturquette@baylibre.com" , "sboyd@kernel.org" , "matthias.bgg@gmail.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" Cc: "p.zabel@pengutronix.de" , "angelogioacchino.delregno@collabora.com" , =?UTF-8?B?Q2h1bi1KaWUgQ2hlbiAo6Zmz5rWa5qGAKQ==?= , "wenst@chromium.org" , =?UTF-8?B?UnVueWFuZyBDaGVuICjpmYjmtqbmtIsp?= , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , Project_Global_Chrome_Upstream_Group References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> <20220422060152.13534-13-rex-bc.chen@mediatek.com> <5ec37a01b0b84140a7d171b9a5cff7ad8f9fbe87.camel@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <5ec37a01b0b84140a7d171b9a5cff7ad8f9fbe87.camel@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 25/04/2022 07:01, Rex-BC Chen wrote: > On Sat, 2022-04-23 at 18:28 +0800, Krzysztof Kozlowski wrote: >> On 22/04/2022 08:01, Rex-BC Chen wrote: >>> To support reset of infra_ao, add the bit definition for >>> thermal/PCIe/SVS. >>> >>> Signed-off-by: Rex-BC Chen >>> --- >>> include/dt-bindings/reset/mt8192-resets.h | 10 ++++++++++ >>> 1 file changed, 10 insertions(+) >>> >>> diff --git a/include/dt-bindings/reset/mt8192-resets.h >>> b/include/dt-bindings/reset/mt8192-resets.h >>> index be9a7ca245b9..d5f3433175c1 100644 >>> --- a/include/dt-bindings/reset/mt8192-resets.h >>> +++ b/include/dt-bindings/reset/mt8192-resets.h >>> @@ -27,4 +27,14 @@ >>> >>> #define MT8192_TOPRGU_SW_RST_NUM 23 >>> >>> +/* INFRA RST0 */ >>> +#define MT8192_INFRA_RST0_LVTS_AP_RST >>> 0 >>> +/* INFRA RST2 */ >>> +#define MT8192_INFRA_RST2_PCIE_PHY_RST >>> 15 >>> +/* INFRA RST3 */ >>> +#define MT8192_INFRA_RST3_PTP_RST 5 >>> +/* INFRA RST4 */ >>> +#define MT8192_INFRA_RST4_LVTS_MCU 12 >>> +#define MT8192_INFRA_RST4_PCIE_TOP 1 >> >> These should be the IDs of reset, not some register values/offsets. >> Therefore it is expected to have them incremented by 1. >> >> > > Hello Krzysztof, > > This is define bit. > > There is serveral reset set for infra_ao while it's not serial. > For MT8192, it's 0x120/0x130/0x140/0x150/0x730. > We are implement #reset-cells = <2>, and we can use this reset drive > more easier. > > For example, in dts, we can define > infra_ao: syscon { > compatible = "mediatek,mt8192-infracfg", "syscon"; > reg = <0 0x10001000 0 0x1000>; > #clock-cells = <1>; > #reset-cells = <2>; > }; > > thermal { > ... > resets = <&infra_ao 0x730 MT8192_INFRA_RST4_LVTS_MCU>; > ... > }; > > If it's acceptabel, I can update all bit difinition from 0 to 15 for > all reset set. Bits are not acceptable, because you embed specific device programming model (register bits) into the binding. These should be IDs, so decimal numbers incremented from 0, so: #define MT8192_INFRA_RST0_LVTS_AP_RST 0 #define MT8192_INFRA_RST4_LVTS_MCU 1 #define MT8192_INFRA_RST4_PCIE_TOP 2 And what is 0x730 in your example? It does not look like ID of a reset... Entire changeset look wrong from DT point of view. Best regards, Krzysztof