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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id gv57-20020a1709072bf900b007acd04fcedcsm1835308ejc.46.2022.11.06.01.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 01:09:18 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Samuel Holland , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Andre Przywara Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng , Gregory CLEMENT , linux-i2c@vger.kernel.org Subject: Re: [PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes Date: Sun, 06 Nov 2022 09:09:17 +0100 Message-ID: <4223066.ejJDZkT8p0@jernej-laptop> In-Reply-To: <20221101141658.3631342-5-andre.przywara@arm.com> References: <20221101141658.3631342-1-andre.przywara@arm.com> <20221101141658.3631342-5-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Dne torek, 01. november 2022 ob 15:16:53 CET je Andre Przywara napisal(a): > The Allwinner F1C100s series of SoCs contain three I2C controllers > compatible to the ones used in other Allwinner SoCs. > > Add the DT nodes describing the resources of the controllers. > I2C1 has only one possible pinmux, so add the pinctrl properties for > that already. > At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so > include those pins already, to simplify referencing them later. > > Signed-off-by: Andre Przywara > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 50 ++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d5a6324e76465..2901c586971b4 > 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -166,6 +166,18 @@ mmc0_pins: mmc0-pins { > drive-strength = <30>; > }; > > + /omit-if-no-ref/ > + i2c0_pd_pins: i2c0-pd-pins { > + pins = "PD0", "PD12"; > + function = "i2c0"; > + }; > + > + /omit-if-no-ref/ Above flag is meaningless if i2c1_pins is always referenced by i2c1. Anyway, I see in pinctrl driver that there are actually two possible pin assignments for i2c1. One on port D and another on port B. Best regards, Jernej > + i2c1_pins: i2c1-pins { > + pins = "PD5", "PD6"; > + function = "i2c1"; > + }; > + > spi0_pc_pins: spi0-pc-pins { > pins = "PC0", "PC1", "PC2", "PC3"; > function = "spi0"; > @@ -177,6 +189,44 @@ uart0_pe_pins: uart0-pe-pins { > }; > }; > > + i2c0: i2c@1c27000 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27000 0x400>; > + interrupts = <7>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@1c27400 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27400 0x400>; > + interrupts = <8>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&i2c1_pins>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@1c27800 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27800 0x400>; > + interrupts = <9>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > timer@1c20c00 { > compatible = "allwinner,suniv-f1c100s- timer"; > reg = <0x01c20c00 0x90>;