Re: [PATCH v2 4/5] phy/rockchip: inno-dsidphy: Add support for rk3568

["Heiko Stübner" <heiko@sntech.de>]

Am Dienstag, 6. September 2022, 19:48:22 CEST schrieb Chris Morgan:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Add support for the Rockchip RK3568 DSI-DPHY. Registers were taken from
> the BSP kernel driver and wherever possible cross referenced with the
> TRM.

With the amount of refactoring done below, I'd expect a bit more
introductory text here ;-)

I.e. about older variants of the phy only supporting 1GHz rates and
newer ones supporting up to 2.5GHz and that you refactor some things
to make both variants work.

> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
>  .../phy/rockchip/phy-rockchip-inno-dsidphy.c  | 204 ++++++++++++++----
>  1 file changed, 158 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> index 630e01b5c19b..2c5847faff63 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> @@ -84,9 +84,25 @@
>  #define DATA_LANE_0_SKEW_PHASE_MASK		GENMASK(2, 0)
>  #define DATA_LANE_0_SKEW_PHASE(x)		UPDATE(x, 2, 0)
>  /* Analog Register Part: reg08 */
> +#define PLL_POST_DIV_ENABLE_MASK		BIT(5)
> +#define PLL_POST_DIV_ENABLE			BIT(5)
>  #define SAMPLE_CLOCK_DIRECTION_MASK		BIT(4)
>  #define SAMPLE_CLOCK_DIRECTION_REVERSE		BIT(4)
>  #define SAMPLE_CLOCK_DIRECTION_FORWARD		0
> +#define LOWFRE_EN_MASK				BIT(5)

PLL_POST_DIR_ENABLE above also is BIT(5) ... is this correct?


otherwise the changes look great.

Heiko