Re: [PATCH v4] ARM: dts: add DT for lan966 SoC and 2-port board pcb8291

[<Tudor.Ambarus@microchip.com>]

On 2/9/22 13:13, Kavyasree Kotagiri wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> This patch adds basic DT for Microchip lan966x SoC and associated board
> pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt
> Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs.
> Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG
> and MCAN0.
> 
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
> ---
> v3 -> v4:
> - Removed character 'x' from compatible string.
> - Removed memory node as handled by bootloader.
> - Renamed flexcom3 usart0 to usart3
> - Added /chosen and /aliases nodes in dts file.
> 
> v2 -> v3:
> - Enabling trng in dtsi itself.
> - Removed "status=okay" dma0.
> - Add gpio pin settings for can0(missed adding this in previous version)
> 
> v1 -> v2:
> - Moved flx3 usart0 node to dtsi file.
> - Removed status="okay" for dma0 to maintain consistency across nodes
>   (which means enabling dma0 by default)
> 
>  arch/arm/boot/dts/Makefile            |   2 +
>  arch/arm/boot/dts/lan966x.dtsi        | 237 ++++++++++++++++++++++++++
>  arch/arm/boot/dts/lan966x_pcb8291.dts |  61 +++++++
>  3 files changed, 300 insertions(+)
>  create mode 100644 arch/arm/boot/dts/lan966x.dtsi
>  create mode 100644 arch/arm/boot/dts/lan966x_pcb8291.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 235ad559acb2..2040a990f08c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
>  dtb-$(CONFIG_SOC_IMX7ULP) += \
>         imx7ulp-com.dtb \
>         imx7ulp-evk.dtb
> +dtb-$(CONFIG_SOC_LAN966) += \
> +       lan966x_pcb8291.dtb
>  dtb-$(CONFIG_SOC_LS1021A) += \
>         ls1021a-moxa-uc-8410a.dtb \
>         ls1021a-qds.dtb \
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> new file mode 100644
> index 000000000000..91ee9e0684f4
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -0,0 +1,237 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
> + *
> + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
> + *
> + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/microchip,lan966x.h>
> +
> +/ {
> +       model = "Microchip LAN966 family SoC";
> +       compatible = "microchip,lan966";
> +       interrupt-parent = <&gic>;
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a7";
> +                       clock-frequency = <600000000>;
> +                       reg = <0x0>;
> +               };
> +       };
> +
> +       clocks {
> +               sys_clk: sys_clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <162500000>;
> +               };
> +
> +               cpu_clk: cpu_clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <600000000>;
> +               };
> +
> +               ddr_clk: ddr_clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <300000000>;
> +               };
> +
> +               nic_clk: nic_clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <200000000>;
> +               };
> +       };
> +
> +       clks: clock-controller@e00c00a8 {
> +               compatible = "microchip,lan966x-gck";
> +               #clock-cells = <1>;
> +               clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
> +               clock-names = "cpu", "ddr", "sys";
> +               reg = <0xe00c00a8 0x38>;
> +       };
> +
> +       timer {
> +               compatible = "arm,armv7-timer";
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> +               clock-frequency = <37500000>;
> +               arm,cpu-registers-not-fw-configured;
> +       };
> +
> +       soc {
> +               compatible = "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges;
> +
> +               flx0: flexcom@e0040000 {
> +                       compatible = "atmel,sama5d2-flexcom";
> +                       reg = <0xe0040000 0x100>;
> +                       clocks = <&clks GCK_ID_FLEXCOM0>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0x0 0xe0040000 0x800>;
> +                       status = "disabled";
> +               };
> +
> +               flx1: flexcom@e0044000 {
> +                       compatible = "atmel,sama5d2-flexcom";
> +                       reg = <0xe0044000 0x100>;
> +                       clocks = <&clks GCK_ID_FLEXCOM1>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0x0 0xe0044000 0x800>;
> +                       status = "disabled";
> +               };
> +
> +               trng: trng@e0048000 {
> +                       compatible = "atmel,at91sam9g45-trng";
> +                       reg = <0xe0048000 0x100>;
> +                       clocks = <&nic_clk>;
> +               };
> +
> +               aes: aes@e004c000 {

Use generic names for nodes, so that we follow the dt node name recommendation.
Use aes: crypto@e004c000. you can find dt specification at
https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.4-rc1

You can check
https://lore.kernel.org/lkml/20220208111225.234685-1-tudor.ambarus@microchip.com/
for reference. Also, please check other node names as well. On a quick look "trng"
should be replaced with "rng".

cheers,
ta