[PATCH v1 2/3] riscv: dts: allwinner: d1: Add thermal sensor and thermal zone

Maksim Kiselev
2023-06-10T14:18:26Z

From: Maxim Kiselev <bigunclemax@gmail.com>

This patch adds a thermal sensor controller node for the D1/T113s.
Also it adds a THS calibration data cell and thermal zone.

Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
---
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 922e8e0e2c09..b893f3325554 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun20i-d1-ccu.h>
#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>

/ {
#address-cells = <1>;
@@ -138,6 +139,19 @@ ccu: clock-controller@2001000 {
#reset-cells = <1>;
};

+ ths: thermal-sensor@2009400 {
+ compatible = "allwinner,sun20i-d1-ths";
+ reg = <0x02009400 0x400>;
+ interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_THS>;
+ clock-names = "bus";
+ resets = <&ccu RST_BUS_THS>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ status = "disabled";
+ #thermal-sensor-cells = <0>;
+ };
+
dmic: dmic@2031000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
@@ -365,6 +379,10 @@ sid: efuse@3006000 {
reg = <0x3006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@14 {
+ reg = <0x14 0x4>;
+ };
};

crypto: crypto@3040000 {
@@ -843,4 +861,12 @@ rtc: rtc@7090000 {
#clock-cells = <1>;
};
};
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+ };
+ };
};
--
2.39.2