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[85.85.171.48]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47aa0960634sm27008175f8f.26.2026.07.06.08.20.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jul 2026 08:20:48 -0700 (PDT) Message-ID: <42e9c942-5b96-4cd4-a25b-51d1a7e8eff7@suse.com> Date: Mon, 6 Jul 2026 17:20:43 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] pmdomain: mediatek: Add support for Direct CTL simple power sequence To: AngeloGioacchino Del Regno , ulfh@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, nfraprado@collabora.com, irving-ch.lin@mediatek.com, macpaul.lin@mediatek.com, aford173@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, justin.yeh@mediatek.com, kernel@collabora.com References: <20260701121920.19347-1-angelogioacchino.delregno@collabora.com> <20260701121920.19347-4-angelogioacchino.delregno@collabora.com> Content-Language: en-US, ca-ES, es-ES From: Matthias Brugger Autocrypt: addr=mbrugger@suse.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 01/07/2026 14:19, AngeloGioacchino Del Regno wrote: > Some new SoCs like MT8196, MT6991, and others, have got one > additional power controller (usually in the HFRP Multimedia > block) which needs a simplified power on/off sequence while > using Direct Control strategy. > > Domains using the "simple power sequence" are not backed by > the RTFF hardware, have no Bus Protection mechanism, lacks > the ISO, PWR_ON, PWR_ON_2ND bits, and therefore get enabled > automatically after getting out of reset. > > This simple power sequence is then a subset of the full one > as only needs the enablement of the specific power domain's > clock input and reset (where, again, after getting out of > reset, the ISO and PWR_ON bits are automatically internally > getting flipped) to enable or disable (power on or off). > > Moreover, the simple power sequence power domains guarantee > that they always get enabled/disabled after executing the > relevant power sequence (on/off) so, differently from the > others, there is also no need to poll for a PWR_ACK. > > Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger > --- > drivers/pmdomain/mediatek/mtk-pm-domains.c | 87 ++++++++++++++++++---- > drivers/pmdomain/mediatek/mtk-pm-domains.h | 1 + > 2 files changed, 72 insertions(+), 16 deletions(-) > > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c > index db543d4b1813..5276adea1d04 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c > @@ -549,9 +549,11 @@ static int scpsys_ctl_pwrseq_on(struct scpsys_domain *pd) > return 0; > } > > -static void scpsys_ctl_pwrseq_off(struct scpsys_domain *pd) > +static int scpsys_ctl_pwrseq_off(struct scpsys_domain *pd) > { > struct scpsys *scpsys = pd->scpsys; > + bool tmp; > + int ret; > > switch (pd->data->rtff_type) { > case SCPSYS_RTFF_TYPE_GENERIC: > @@ -583,6 +585,41 @@ static void scpsys_ctl_pwrseq_off(struct scpsys_domain *pd) > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); > + > + /* wait until PWR_ACK = 0 */ > + ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_DELAY_US, > + MTK_POLL_TIMEOUT); > + if (ret < 0) > + return ret; > + > + return 0; > +} > + > +static int scpsys_simple_pwrseq_on(struct scpsys_domain *pd) > +{ > + struct scpsys *scpsys = pd->scpsys; > + > + /* Enable subsys clock input and trigger power domain reset state */ > + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); > + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > + > + /* Wait for the hardware to stabilize */ > + udelay(1); > + > + /* Get out of reset: set power on */ > + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > + > + return 0; > +} > + > +static int scpsys_simple_pwrseq_off(struct scpsys_domain *pd) > +{ > + struct scpsys *scpsys = pd->scpsys; > + > + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); > + > + return 0; > } > > static int scpsys_modem_pwrseq_on(struct scpsys_domain *pd) > @@ -605,14 +642,24 @@ static int scpsys_modem_pwrseq_on(struct scpsys_domain *pd) > return 0; > } > > -static void scpsys_modem_pwrseq_off(struct scpsys_domain *pd) > +static int scpsys_modem_pwrseq_off(struct scpsys_domain *pd) > { > struct scpsys *scpsys = pd->scpsys; > + bool tmp; > + int ret; > > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); > > if (!MTK_SCPD_CAPS(pd, MTK_SCPD_SKIP_RESET_B)) > regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); > + > + /* wait until PWR_ACK = 0 */ > + ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_DELAY_US, > + MTK_POLL_TIMEOUT); > + if (ret < 0) > + return ret; > + > + return 0; > } > > static int scpsys_power_on(struct generic_pm_domain *genpd) > @@ -635,6 +682,8 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > > if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ)) > ret = scpsys_modem_pwrseq_on(pd); > + else if (MTK_SCPD_CAPS(pd, MTK_SCPD_SIMPLE_PWRSEQ)) > + ret = scpsys_simple_pwrseq_on(pd); > else > ret = scpsys_ctl_pwrseq_on(pd); > > @@ -662,9 +711,11 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > goto err_pwr_ack; > } > > - ret = scpsys_sram_enable(pd); > - if (ret < 0) > - goto err_disable_subsys_clks; > + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_SIMPLE_PWRSEQ)) { > + ret = scpsys_sram_enable(pd); > + if (ret < 0) > + goto err_disable_subsys_clks; > + } > > ret = scpsys_bus_protect_disable(pd, 0); > if (ret < 0) > @@ -682,7 +733,8 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > err_enable_bus_protect: > scpsys_bus_protect_enable(pd, 0); > err_disable_sram: > - scpsys_sram_disable(pd); > + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_SIMPLE_PWRSEQ)) > + scpsys_sram_disable(pd); > err_disable_subsys_clks: > if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) > clk_bulk_disable_unprepare(pd->num_subsys_clks, > @@ -698,16 +750,17 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) > { > struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd); > struct scpsys *scpsys = pd->scpsys; > - bool tmp; > int ret; > > ret = scpsys_bus_protect_enable(pd, 0); > if (ret < 0) > return ret; > > - ret = scpsys_sram_disable(pd); > - if (ret < 0) > - return ret; > + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_SIMPLE_PWRSEQ)) { > + ret = scpsys_sram_disable(pd); > + if (ret < 0) > + return ret; > + } > > if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO)) > regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs, > @@ -721,15 +774,11 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) > > if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ)) > scpsys_modem_pwrseq_off(pd); > + else if (MTK_SCPD_CAPS(pd, MTK_SCPD_SIMPLE_PWRSEQ)) > + ret = scpsys_simple_pwrseq_off(pd); > else > scpsys_ctl_pwrseq_off(pd); > > - /* wait until PWR_ACK = 0 */ > - ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_DELAY_US, > - MTK_POLL_TIMEOUT); > - if (ret < 0) > - return ret; > - > clk_bulk_disable_unprepare(pd->num_clks, pd->clks); > > scpsys_regulator_disable(pd->supply); > @@ -1083,6 +1132,12 @@ static int scpsys_get_bus_protection_legacy(struct device *dev, struct scpsys *s > regmap[2] = NULL; > } > > + /* If no access controllers are needed, don't allocate and don't fail */ > + if (num_regmaps == 0) { > + scpsys->bus_prot = NULL; > + return 0; > + } > + > scpsys->bus_prot = devm_kmalloc_array(dev, num_regmaps, > sizeof(*scpsys->bus_prot), GFP_KERNEL); > if (!scpsys->bus_prot) > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h > index a5dca24cbc2f..092403de66fa 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h > @@ -17,6 +17,7 @@ > #define MTK_SCPD_MODEM_PWRSEQ BIT(10) > #define MTK_SCPD_SKIP_RESET_B BIT(11) > #define MTK_SCPD_INFRA_PWR_CTL BIT(12) > +#define MTK_SCPD_SIMPLE_PWRSEQ BIT(13) > #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data ? \ > (_scpd)->data->caps & (_x) : \ > (_scpd)->hwv_data->caps & (_x))