* [PATCH v3 1/5] dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt names
2023-07-27 8:18 [PATCH v3 0/5] Add RZ/G2UL MTU3a support Biju Das
@ 2023-07-27 8:18 ` Biju Das
2023-07-27 8:18 ` [PATCH v3 2/5] dt-bindings: timer: renesas,rz-mtu3: Improve documentation Biju Das
` (5 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2023-07-27 8:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven,
Magnus Damm, Lee Jones, linux-iio, linux-renesas-soc, devicetree,
Fabrizio Castro, Prabhakar Mahadev Lad, stable, Conor Dooley
As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow
interrupt names starts with 'tci' instead of 'tgi'.
Fix this documentation issue by replacing below overflow/underflow
interrupt names:
- tgiv0->tciv0
- tgiv1->tciv1
- tgiu1->tciu1
- tgiv2->tciv2
- tgiu2->tciu2
- tgiv3->tciv3
- tgiv4->tciv4
- tgiv6->tciv6
- tgiv7->tciv7
- tgiv8->tciv8
- tgiu8->tciu8
Fixes: 0a9d6b54297e ("dt-bindings: timer: Document RZ/G2L MTU3a bindings")
Cc: stable@kernel.org
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2->v3:
* Added Rb tag from Geert.
v1->v2:
* Added Ack from Conor Dooley.
---
.../bindings/timer/renesas,rz-mtu3.yaml | 38 +++++++++----------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index bffdab0b0185..fbac40b958dd 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -169,27 +169,27 @@ properties:
- const: tgib0
- const: tgic0
- const: tgid0
- - const: tgiv0
+ - const: tciv0
- const: tgie0
- const: tgif0
- const: tgia1
- const: tgib1
- - const: tgiv1
- - const: tgiu1
+ - const: tciv1
+ - const: tciu1
- const: tgia2
- const: tgib2
- - const: tgiv2
- - const: tgiu2
+ - const: tciv2
+ - const: tciu2
- const: tgia3
- const: tgib3
- const: tgic3
- const: tgid3
- - const: tgiv3
+ - const: tciv3
- const: tgia4
- const: tgib4
- const: tgic4
- const: tgid4
- - const: tgiv4
+ - const: tciv4
- const: tgiu5
- const: tgiv5
- const: tgiw5
@@ -197,18 +197,18 @@ properties:
- const: tgib6
- const: tgic6
- const: tgid6
- - const: tgiv6
+ - const: tciv6
- const: tgia7
- const: tgib7
- const: tgic7
- const: tgid7
- - const: tgiv7
+ - const: tciv7
- const: tgia8
- const: tgib8
- const: tgic8
- const: tgid8
- - const: tgiv8
- - const: tgiu8
+ - const: tciv8
+ - const: tciu8
clocks:
maxItems: 1
@@ -285,16 +285,16 @@ examples:
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0",
"tgif0",
- "tgia1", "tgib1", "tgiv1", "tgiu1",
- "tgia2", "tgib2", "tgiv2", "tgiu2",
- "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
- "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
+ "tgia3", "tgib3", "tgic3", "tgid3", "tciv3",
+ "tgia4", "tgib4", "tgic4", "tgid4", "tciv4",
"tgiu5", "tgiv5", "tgiw5",
- "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
- "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
- "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
+ "tgia6", "tgib6", "tgic6", "tgid6", "tciv6",
+ "tgia7", "tgib7", "tgic7", "tgid7", "tciv7",
+ "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 2/5] dt-bindings: timer: renesas,rz-mtu3: Improve documentation
2023-07-27 8:18 [PATCH v3 0/5] Add RZ/G2UL MTU3a support Biju Das
2023-07-27 8:18 ` [PATCH v3 1/5] dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt names Biju Das
@ 2023-07-27 8:18 ` Biju Das
2023-07-27 8:18 ` [PATCH v3 3/5] dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs Biju Das
` (4 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2023-07-27 8:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven,
Magnus Damm, linux-iio, linux-renesas-soc, devicetree,
Fabrizio Castro, Prabhakar Mahadev Lad, Pavel Machek,
Conor Dooley
Fix the documentation issues pointed by Pavel while backporting
it to 6.1.y-cip.
- Replace '32- bit'->'32-bit'
- Consistently remove '.' at the end of line for the specifications
- Replace ' (excluding MTU8)'-> '(excluding MTU8)'
Reported-by: Pavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/all/ZH79%2FUjgYg+0Ruiu@duo.ucw.cz
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v2->v3:
* Updated the link to lore for Closes tag.
v1->v2:
* Added Ack by Conor Dooley
---
.../bindings/timer/renesas,rz-mtu3.yaml | 28 +++++++++----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index fbac40b958dd..670a2ebaacdb 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -11,8 +11,8 @@ maintainers:
description: |
This hardware block consists of eight 16-bit timer channels and one
- 32- bit timer channel. It supports the following specifications:
- - Pulse input/output: 28 lines max.
+ 32-bit timer channel. It supports the following specifications:
+ - Pulse input/output: 28 lines max
- Pulse input 3 lines
- Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
@@ -23,11 +23,11 @@ description: |
- Input capture function (noise filter setting available)
- Counter-clearing operation
- Simultaneous writing to multiple timer counters (TCNT)
- (excluding MTU8).
+ (excluding MTU8)
- Simultaneous clearing on compare match or input capture
- (excluding MTU8).
+ (excluding MTU8)
- Simultaneous input and output to registers in synchronization with
- counter operations (excluding MTU8).
+ counter operations (excluding MTU8)
- Up to 12-phase PWM output in combination with synchronous operation
(excluding MTU8)
- [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
@@ -40,26 +40,26 @@ description: |
- [MTU3, MTU4, MTU6, and MTU7]
- Through interlocked operation of MTU3/4 and MTU6/7, the positive and
negative signals in six phases (12 phases in total) can be output in
- complementary PWM and reset-synchronized PWM operation.
+ complementary PWM and reset-synchronized PWM operation
- In complementary PWM mode, values can be transferred from buffer
registers to temporary registers at crests and troughs of the timer-
counter values or when the buffer registers (TGRD registers in MTU4
- and MTU7) are written to.
- - Double-buffering selectable in complementary PWM mode.
+ and MTU7) are written to
+ - Double-buffering selectable in complementary PWM mode
- [MTU3 and MTU4]
- Through interlocking with MTU0, a mode for driving AC synchronous
motors (brushless DC motors) by using complementary PWM output and
reset-synchronized PWM output is settable and allows the selection
- of two types of waveform output (chopping or level).
+ of two types of waveform output (chopping or level)
- [MTU5]
- - Capable of operation as a dead-time compensation counter.
+ - Capable of operation as a dead-time compensation counter
- [MTU0/MTU5, MTU1, MTU2, and MTU8]
- 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
- through interlocked operation with MTU0/MTU5 and MTU8.
+ through interlocked operation with MTU0/MTU5 and MTU8
- Interrupt-skipping function
- In complementary PWM mode, interrupts on crests and troughs of counter
values and triggers to start conversion by the A/D converter can be
- skipped.
+ skipped
- Interrupt sources: 43 sources.
- Buffer operation:
- Automatic transfer of register data (transfer from the buffer
@@ -68,9 +68,9 @@ description: |
- A/D converter start triggers can be generated
- A/D converter start request delaying function enables A/D converter
to be started with any desired timing and to be synchronized with
- PWM output.
+ PWM output
- Low power consumption function
- - The MTU3a can be placed in the module-stop state.
+ - The MTU3a can be placed in the module-stop state
There are two phase counting modes. 16-bit phase counting mode in which
MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 3/5] dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
2023-07-27 8:18 [PATCH v3 0/5] Add RZ/G2UL MTU3a support Biju Das
2023-07-27 8:18 ` [PATCH v3 1/5] dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt names Biju Das
2023-07-27 8:18 ` [PATCH v3 2/5] dt-bindings: timer: renesas,rz-mtu3: Improve documentation Biju Das
@ 2023-07-27 8:18 ` Biju Das
2023-07-27 8:18 ` [PATCH v3 4/5] arm64: dts: renesas: r9a07g043: Add MTU3a node Biju Das
` (3 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2023-07-27 8:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, Daniel Lezcano, Thomas Gleixner, Geert Uytterhoeven,
Magnus Damm, linux-iio, linux-renesas-soc, devicetree,
Fabrizio Castro, Prabhakar Mahadev Lad, Conor Dooley
Add MTU3a binding documentation for Renesas RZ/{G2UL,Five} SoCs.
MTU3a block is identical to one found on RZ/G2L, so no driver changes are
required. The fallback compatible string "renesas,rz-mtu3" will be used
on RZ/{G2UL,Five}.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2->v3:
* Added Rb tag from Geert.
* Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
* Updated commit header and description.
* Retained tags as it is trivial change.
v1->v2:
* Added ack from Conor Dooley.
---
Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index 670a2ebaacdb..3931054b42fb 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -109,6 +109,7 @@ properties:
compatible:
items:
- enum:
+ - renesas,r9a07g043-mtu3 # RZ/{G2UL,Five}
- renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
- renesas,r9a07g054-mtu3 # RZ/V2L
- const: renesas,rz-mtu3
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 4/5] arm64: dts: renesas: r9a07g043: Add MTU3a node
2023-07-27 8:18 [PATCH v3 0/5] Add RZ/G2UL MTU3a support Biju Das
` (2 preceding siblings ...)
2023-07-27 8:18 ` [PATCH v3 3/5] dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs Biju Das
@ 2023-07-27 8:18 ` Biju Das
2023-07-27 12:22 ` Geert Uytterhoeven
2023-07-27 8:18 ` [PATCH v3 5/5] arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3 Biju Das
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Biju Das @ 2023-07-27 8:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Fabrizio Castro, Prabhakar Mahadev Lad
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* No change
v1->v2:
* Updated commit description RZ/G2UL->RZ/{G2UL,Five}.
* Fixed build error reported by kernel test robot by replacing
GIC_SPI x ->SOC_PERIPHERAL_IRQ(x).
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 27c35a657b15..8721f4c9fa0f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -74,6 +74,76 @@ soc: soc {
#size-cells = <2>;
ranges;
+ mtu3: timer@10001200 {
+ compatible = "renesas,r9a07g043-mtu3",
+ "renesas,rz-mtu3";
+ reg = <0 0x10001200 0 0xb00>;
+ interrupts = <SOC_PERIPHERAL_IRQ(170) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(171) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(172) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(173) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(174) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(175) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(176) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(177) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(178) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(179) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(180) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(181) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(182) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(183) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(184) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(185) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(186) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(187) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(188) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(189) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(190) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(191) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(192) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(193) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(194) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(195) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(196) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(197) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(198) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(199) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(200) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(201) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(202) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(203) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(204) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(205) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(206) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(207) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(208) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
+ "tgia3", "tgib3", "tgic3", "tgid3",
+ "tciv3",
+ "tgia4", "tgib4", "tgic4", "tgid4",
+ "tciv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6",
+ "tciv6",
+ "tgia7", "tgib7", "tgic7", "tgid7",
+ "tciv7",
+ "tgia8", "tgib8", "tgic8", "tgid8",
+ "tciv8", "tciu8";
+ clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 4/5] arm64: dts: renesas: r9a07g043: Add MTU3a node
2023-07-27 8:18 ` [PATCH v3 4/5] arm64: dts: renesas: r9a07g043: Add MTU3a node Biju Das
@ 2023-07-27 12:22 ` Geert Uytterhoeven
0 siblings, 0 replies; 16+ messages in thread
From: Geert Uytterhoeven @ 2023-07-27 12:22 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm,
linux-renesas-soc, devicetree, Fabrizio Castro,
Prabhakar Mahadev Lad
On Thu, Jul 27, 2023 at 10:19 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
> * No change
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 5/5] arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
2023-07-27 8:18 [PATCH v3 0/5] Add RZ/G2UL MTU3a support Biju Das
` (3 preceding siblings ...)
2023-07-27 8:18 ` [PATCH v3 4/5] arm64: dts: renesas: r9a07g043: Add MTU3a node Biju Das
@ 2023-07-27 8:18 ` Biju Das
2023-07-27 12:22 ` Geert Uytterhoeven
2023-08-31 16:08 ` [PATCH v3 0/5] Add RZ/G2UL MTU3a support Conor Dooley
2023-10-09 14:28 ` Daniel Lezcano
6 siblings, 1 reply; 16+ messages in thread
From: Biju Das @ 2023-07-27 8:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Fabrizio Castro, Prabhakar Mahadev Lad
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2UL SMARC
EVK.
The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when
PMOD_MTU3 macro is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* No change
v1->v2:
* No change.
---
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 11 +++++++++++
.../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 6 ++++++
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 13 +++++++++++++
3 files changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 01483b4302c2..8e0107df2d46 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -17,6 +17,17 @@
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * - Set DIP-Switch SW1-3 to On position.
+ * - Set PMOD_MTU3 macro to 1.
+ */
+#define PMOD_MTU3 0
+
+#if (PMOD_MTU3 && !SW_ET0_EN_N)
+#error "Cannot set as both PMOD_MTU3 and !SW_ET0_EN_N are mutually exclusive"
+#endif
+
#include "r9a07g043u.dtsi"
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
index 58923dc83faa..355694fe4af6 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
@@ -50,6 +50,12 @@ i2c1_pins: i2c1 {
input-enable;
};
+ mtu3_pins: mtu3 {
+ mtu2-pwm {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 4)>; /* MTIOC2A */
+ };
+ };
+
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
<RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
index 2a1331ed1a5c..8eb411aac80d 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
@@ -28,6 +28,19 @@ wm8978: codec@1a {
};
};
+#if PMOD_MTU3
+&mtu3 {
+ pinctrl-0 = <&mtu3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&spi1 {
+ status = "disabled";
+};
+#endif
+
#if (SW_ET0_EN_N)
&ssi1 {
pinctrl-0 = <&ssi1_pins>;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 5/5] arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
2023-07-27 8:18 ` [PATCH v3 5/5] arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3 Biju Das
@ 2023-07-27 12:22 ` Geert Uytterhoeven
0 siblings, 0 replies; 16+ messages in thread
From: Geert Uytterhoeven @ 2023-07-27 12:22 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm,
linux-renesas-soc, devicetree, Fabrizio Castro,
Prabhakar Mahadev Lad
On Thu, Jul 27, 2023 at 10:19 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2UL SMARC
> EVK.
>
> The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when
> PMOD_MTU3 macro is enabled.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
> * No change
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.6.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-07-27 8:18 [PATCH v3 0/5] Add RZ/G2UL MTU3a support Biju Das
` (4 preceding siblings ...)
2023-07-27 8:18 ` [PATCH v3 5/5] arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3 Biju Das
@ 2023-08-31 16:08 ` Conor Dooley
2023-09-18 8:04 ` Biju Das
2023-10-09 14:28 ` Daniel Lezcano
6 siblings, 1 reply; 16+ messages in thread
From: Conor Dooley @ 2023-08-31 16:08 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daniel Lezcano,
Thomas Gleixner, Geert Uytterhoeven, Magnus Damm, linux-iio,
linux-renesas-soc, devicetree, Fabrizio Castro,
Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1290 bytes --]
On Thu, Jul 27, 2023 at 09:18:43AM +0100, Biju Das wrote:
> This patch series aims to add MTU3a support for RZ/G2UL SMARC EVK.
> Also it fixes overflow/underflow interrupt names.
>
> v2->v3:
> * Dropped patch#4, as it accepted for 6.5 fixes.
> * Moved patch#2 to patch#1 as it is fixes patch.
> * Added Rb tag from Geert for patch#1 and patch#3.
> * Updated the link to lore for Closes tag for patch#2.
> * Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
>
> v1->v2:
> * Added Ack tags from Conor Dooley for binding patches
> * Updated commit description RZ/G2UL->RZ/{G2UL,Five} for patch#5.
> * Fixed build error reported by kernel test robot by replacing
> GIC_SPI x ->SOC_PERIPHERAL_IRQ(x) for patch#5.
>
> Biju Das (5):
> dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt
> names
> dt-bindings: timer: renesas,rz-mtu3: Improve documentation
> dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
> arm64: dts: renesas: r9a07g043: Add MTU3a node
> arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
I'm seeing dtbs_check issues in next & Linus' tree as the binding
patches for this don't seem to have landed.
What's the craic with getting them applied?
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-08-31 16:08 ` [PATCH v3 0/5] Add RZ/G2UL MTU3a support Conor Dooley
@ 2023-09-18 8:04 ` Biju Das
2023-10-09 6:54 ` Biju Das
0 siblings, 1 reply; 16+ messages in thread
From: Biju Das @ 2023-09-18 8:04 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Fabrizio Castro, Prabhakar Mahadev Lad, Conor Dooley
Hi All,
Gentle ping. Are we happy with timer documentation patches
as dts patches hit on 6.6-rc1?
Cheers,
Biju
> On Thu, Jul 27, 2023 at 09:18:43AM +0100, Biju Das wrote:
> > This patch series aims to add MTU3a support for RZ/G2UL SMARC EVK.
> > Also it fixes overflow/underflow interrupt names.
> >
> > v2->v3:
> > * Dropped patch#4, as it accepted for 6.5 fixes.
> > * Moved patch#2 to patch#1 as it is fixes patch.
> > * Added Rb tag from Geert for patch#1 and patch#3.
> > * Updated the link to lore for Closes tag for patch#2.
> > * Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
> >
> > v1->v2:
> > * Added Ack tags from Conor Dooley for binding patches
> > * Updated commit description RZ/G2UL->RZ/{G2UL,Five} for patch#5.
> > * Fixed build error reported by kernel test robot by replacing
> > GIC_SPI x ->SOC_PERIPHERAL_IRQ(x) for patch#5.
> >
> > Biju Das (5):
> > dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt
> > names
> > dt-bindings: timer: renesas,rz-mtu3: Improve documentation
> > dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
> > arm64: dts: renesas: r9a07g043: Add MTU3a node
> > arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
>
> I'm seeing dtbs_check issues in next & Linus' tree as the binding patches
> for this don't seem to have landed.
> What's the craic with getting them applied?
>
> Thanks,
> Conor.
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-09-18 8:04 ` Biju Das
@ 2023-10-09 6:54 ` Biju Das
2023-10-09 9:52 ` Daniel Lezcano
0 siblings, 1 reply; 16+ messages in thread
From: Biju Das @ 2023-10-09 6:54 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Rob Herring
Cc: Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Fabrizio Castro, Prabhakar Mahadev Lad, Conor Dooley
Hi all,
Gentle ping. This patch is in the patch work for a while.
It is acked/reviewed by Conor Dooley and Geert Uytterhoeven.
Can we apply to mainline if you are happy? Or do you want me
to RESEND the patches? Please let me know.
Cheers,
Biju
>
> > On Thu, Jul 27, 2023 at 09:18:43AM +0100, Biju Das wrote:
> > > This patch series aims to add MTU3a support for RZ/G2UL SMARC EVK.
> > > Also it fixes overflow/underflow interrupt names.
> > >
> > > v2->v3:
> > > * Dropped patch#4, as it accepted for 6.5 fixes.
> > > * Moved patch#2 to patch#1 as it is fixes patch.
> > > * Added Rb tag from Geert for patch#1 and patch#3.
> > > * Updated the link to lore for Closes tag for patch#2.
> > > * Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
> > >
> > > v1->v2:
> > > * Added Ack tags from Conor Dooley for binding patches
> > > * Updated commit description RZ/G2UL->RZ/{G2UL,Five} for patch#5.
> > > * Fixed build error reported by kernel test robot by replacing
> > > GIC_SPI x ->SOC_PERIPHERAL_IRQ(x) for patch#5.
> > >
> > > Biju Das (5):
> > > dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt
> > > names
> > > dt-bindings: timer: renesas,rz-mtu3: Improve documentation
> > > dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
> > > arm64: dts: renesas: r9a07g043: Add MTU3a node
> > > arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-10-09 6:54 ` Biju Das
@ 2023-10-09 9:52 ` Daniel Lezcano
2023-10-09 13:59 ` Conor Dooley
0 siblings, 1 reply; 16+ messages in thread
From: Daniel Lezcano @ 2023-10-09 9:52 UTC (permalink / raw)
To: Biju Das, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski
Cc: Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Fabrizio Castro, Prabhakar Mahadev Lad, Conor Dooley
On 09/10/2023 08:54, Biju Das wrote:
> Hi all,
>
> Gentle ping. This patch is in the patch work for a while.
> It is acked/reviewed by Conor Dooley and Geert Uytterhoeven.
>
> Can we apply to mainline if you are happy? Or do you want me
> to RESEND the patches? Please let me know.
Krzysztof ?
>>> On Thu, Jul 27, 2023 at 09:18:43AM +0100, Biju Das wrote:
>>>> This patch series aims to add MTU3a support for RZ/G2UL SMARC EVK.
>>>> Also it fixes overflow/underflow interrupt names.
>>>>
>>>> v2->v3:
>>>> * Dropped patch#4, as it accepted for 6.5 fixes.
>>>> * Moved patch#2 to patch#1 as it is fixes patch.
>>>> * Added Rb tag from Geert for patch#1 and patch#3.
>>>> * Updated the link to lore for Closes tag for patch#2.
>>>> * Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
>>>>
>>>> v1->v2:
>>>> * Added Ack tags from Conor Dooley for binding patches
>>>> * Updated commit description RZ/G2UL->RZ/{G2UL,Five} for patch#5.
>>>> * Fixed build error reported by kernel test robot by replacing
>>>> GIC_SPI x ->SOC_PERIPHERAL_IRQ(x) for patch#5.
>>>>
>>>> Biju Das (5):
>>>> dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt
>>>> names
>>>> dt-bindings: timer: renesas,rz-mtu3: Improve documentation
>>>> dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
>>>> arm64: dts: renesas: r9a07g043: Add MTU3a node
>>>> arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-10-09 9:52 ` Daniel Lezcano
@ 2023-10-09 13:59 ` Conor Dooley
2023-10-09 14:18 ` Daniel Lezcano
0 siblings, 1 reply; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 13:59 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Biju Das, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm,
linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, Fabrizio Castro,
Prabhakar Mahadev Lad, Conor Dooley
[-- Attachment #1: Type: text/plain, Size: 2079 bytes --]
On Mon, Oct 09, 2023 at 11:52:13AM +0200, Daniel Lezcano wrote:
> On 09/10/2023 08:54, Biju Das wrote:
> > Hi all,
> >
> > Gentle ping. This patch is in the patch work for a while.
> > It is acked/reviewed by Conor Dooley and Geert Uytterhoeven.
> >
> > Can we apply to mainline if you are happy? Or do you want me
> > to RESEND the patches? Please let me know.
>
> Krzysztof ?
Daniel ?
(Or for the non-telepathic, what is "Krzysztof ?" supposed to mean?)
Cheers,
Conor.
> > > > On Thu, Jul 27, 2023 at 09:18:43AM +0100, Biju Das wrote:
> > > > > This patch series aims to add MTU3a support for RZ/G2UL SMARC EVK.
> > > > > Also it fixes overflow/underflow interrupt names.
> > > > >
> > > > > v2->v3:
> > > > > * Dropped patch#4, as it accepted for 6.5 fixes.
> > > > > * Moved patch#2 to patch#1 as it is fixes patch.
> > > > > * Added Rb tag from Geert for patch#1 and patch#3.
> > > > > * Updated the link to lore for Closes tag for patch#2.
> > > > > * Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
> > > > >
> > > > > v1->v2:
> > > > > * Added Ack tags from Conor Dooley for binding patches
> > > > > * Updated commit description RZ/G2UL->RZ/{G2UL,Five} for patch#5.
> > > > > * Fixed build error reported by kernel test robot by replacing
> > > > > GIC_SPI x ->SOC_PERIPHERAL_IRQ(x) for patch#5.
> > > > >
> > > > > Biju Das (5):
> > > > > dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt
> > > > > names
> > > > > dt-bindings: timer: renesas,rz-mtu3: Improve documentation
> > > > > dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
> > > > > arm64: dts: renesas: r9a07g043: Add MTU3a node
> > > > > arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
> >
>
> --
> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-10-09 13:59 ` Conor Dooley
@ 2023-10-09 14:18 ` Daniel Lezcano
2023-10-09 16:17 ` Conor Dooley
0 siblings, 1 reply; 16+ messages in thread
From: Daniel Lezcano @ 2023-10-09 14:18 UTC (permalink / raw)
To: Conor Dooley
Cc: Biju Das, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm,
linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, Fabrizio Castro,
Prabhakar Mahadev Lad, Conor Dooley
On 09/10/2023 15:59, Conor Dooley wrote:
> On Mon, Oct 09, 2023 at 11:52:13AM +0200, Daniel Lezcano wrote:
>> On 09/10/2023 08:54, Biju Das wrote:
>>> Hi all,
>>>
>>> Gentle ping. This patch is in the patch work for a while.
>>> It is acked/reviewed by Conor Dooley and Geert Uytterhoeven.
>>>
>>> Can we apply to mainline if you are happy? Or do you want me
>>> to RESEND the patches? Please let me know.
>>
>> Krzysztof ?
>
> Daniel ?
>
> (Or for the non-telepathic, what is "Krzysztof ?" supposed to mean?)
Sorry I missed you were in the DT bindings maintainer list. I was
expecting Krzysztof tag.
I'll pick the patches now.
Thanks
>>>>> On Thu, Jul 27, 2023 at 09:18:43AM +0100, Biju Das wrote:
>>>>>> This patch series aims to add MTU3a support for RZ/G2UL SMARC EVK.
>>>>>> Also it fixes overflow/underflow interrupt names.
>>>>>>
>>>>>> v2->v3:
>>>>>> * Dropped patch#4, as it accepted for 6.5 fixes.
>>>>>> * Moved patch#2 to patch#1 as it is fixes patch.
>>>>>> * Added Rb tag from Geert for patch#1 and patch#3.
>>>>>> * Updated the link to lore for Closes tag for patch#2.
>>>>>> * Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
>>>>>>
>>>>>> v1->v2:
>>>>>> * Added Ack tags from Conor Dooley for binding patches
>>>>>> * Updated commit description RZ/G2UL->RZ/{G2UL,Five} for patch#5.
>>>>>> * Fixed build error reported by kernel test robot by replacing
>>>>>> GIC_SPI x ->SOC_PERIPHERAL_IRQ(x) for patch#5.
>>>>>>
>>>>>> Biju Das (5):
>>>>>> dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt
>>>>>> names
>>>>>> dt-bindings: timer: renesas,rz-mtu3: Improve documentation
>>>>>> dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
>>>>>> arm64: dts: renesas: r9a07g043: Add MTU3a node
>>>>>> arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
>>>
>>
>> --
>> <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>>
>> Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
>> <http://twitter.com/#!/linaroorg> Twitter |
>> <http://www.linaro.org/linaro-blog/> Blog
>>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-10-09 14:18 ` Daniel Lezcano
@ 2023-10-09 16:17 ` Conor Dooley
0 siblings, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-10-09 16:17 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Conor Dooley, Biju Das, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Fabrizio Castro, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 871 bytes --]
On Mon, Oct 09, 2023 at 04:18:13PM +0200, Daniel Lezcano wrote:
> On 09/10/2023 15:59, Conor Dooley wrote:
> > On Mon, Oct 09, 2023 at 11:52:13AM +0200, Daniel Lezcano wrote:
> > > On 09/10/2023 08:54, Biju Das wrote:
> > > > Hi all,
> > > >
> > > > Gentle ping. This patch is in the patch work for a while.
> > > > It is acked/reviewed by Conor Dooley and Geert Uytterhoeven.
> > > >
> > > > Can we apply to mainline if you are happy? Or do you want me
> > > > to RESEND the patches? Please let me know.
> > >
> > > Krzysztof ?
> >
> > Daniel ?
> >
> > (Or for the non-telepathic, what is "Krzysztof ?" supposed to mean?)
>
> Sorry I missed you were in the DT bindings maintainer list. I was expecting
> Krzysztof tag.
Heh, I figured that that is what was going on, but my telepathy skills
were a bit lacking and I was not 100% sure... NW!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/5] Add RZ/G2UL MTU3a support
2023-07-27 8:18 [PATCH v3 0/5] Add RZ/G2UL MTU3a support Biju Das
` (5 preceding siblings ...)
2023-08-31 16:08 ` [PATCH v3 0/5] Add RZ/G2UL MTU3a support Conor Dooley
@ 2023-10-09 14:28 ` Daniel Lezcano
6 siblings, 0 replies; 16+ messages in thread
From: Daniel Lezcano @ 2023-10-09 14:28 UTC (permalink / raw)
To: Biju Das, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Thomas Gleixner, Geert Uytterhoeven, Magnus Damm, linux-iio,
linux-renesas-soc, devicetree, Fabrizio Castro,
Prabhakar Mahadev Lad
On 27/07/2023 10:18, Biju Das wrote:
> This patch series aims to add MTU3a support for RZ/G2UL SMARC EVK.
> Also it fixes overflow/underflow interrupt names.
>
> v2->v3:
> * Dropped patch#4, as it accepted for 6.5 fixes.
> * Moved patch#2 to patch#1 as it is fixes patch.
> * Added Rb tag from Geert for patch#1 and patch#3.
> * Updated the link to lore for Closes tag for patch#2.
> * Documented RZ/Five SoC as the same IP used in RZ/G2UL SoC.
>
> v1->v2:
> * Added Ack tags from Conor Dooley for binding patches
> * Updated commit description RZ/G2UL->RZ/{G2UL,Five} for patch#5.
> * Fixed build error reported by kernel test robot by replacing
> GIC_SPI x ->SOC_PERIPHERAL_IRQ(x) for patch#5.
>
> Biju Das (5):
> dt-bindings: timer: renesas,rz-mtu3: Fix overflow/underflow interrupt
> names
> dt-bindings: timer: renesas,rz-mtu3: Improve documentation
> dt-bindings: timer: renesas,rz-mtu3: Document RZ/{G2UL,Five} SoCs
> arm64: dts: renesas: r9a07g043: Add MTU3a node
> arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
>
> .../bindings/timer/renesas,rz-mtu3.yaml | 67 +++++++++---------
> arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 70 +++++++++++++++++++
> .../boot/dts/renesas/r9a07g043u11-smarc.dts | 11 +++
> .../dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 6 ++
> arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 13 ++++
> 5 files changed, 134 insertions(+), 33 deletions(-)
>
patches 1,2 and 3 applied
Thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 16+ messages in thread