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On 15/09/2026 19:46, Caleb James DeLisle wrote: > The EcoNet EN751221 has either one, or two, onboard MT7530 switches. > Every implementation of this SoC has one switch on die with the CPU, > but some chips - notably those with a "G" in the name, have a second > MT7530 as an MCM module. > > The on-die MT7530 has 4 FE ports and 1 GE port. The MCM switch has all > gigabit ports. > > The MCM switch connects to the SoC switch via a TRGMII link from port > 5 on the SoC switch to port 6 on the MCM switch. This link undergoes > calibration on startup. > > All known devices with the MCM present do not make any use of the ports > on the on-die switch, it is put into "passthrough" mode in which all > traffic is shuttled between port 6 and port 5 without alteration of the > DSA tags. > > Add support for both the on-die and the MCM switch, and calibration of > the TRGMII link between them. On pcbs with rgmii connected phys there is an optimal delay value where the data line is sampled relative to the clock line. This value depends on the length of the pcb signal trace and is thus a static board property. The same logic should apply to a SoC. Ie per different Econet SoC that implements the MCM companion switch there should be a value that is optimal. Thus I suggest that dts property also is added and that the calibration is performed if that property is not present. The original SDK and production units seem to have a fixed setting and user testing also indicate that a fixed value results in a working trgmii link. MvH Benjamin Larsson