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Wed, 25 Sep 2024 03:47:22 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48P3l93T030053 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Sep 2024 03:47:09 GMT Received: from [10.239.29.179] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 20:47:04 -0700 Message-ID: <4368503f-fb33-4e6a-bef4-517e2b959400@quicinc.com> Date: Wed, 25 Sep 2024 11:47:02 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/6] PCI: qcom: Add support for X1E80100 SoC To: Johan Hovold , Manivannan Sadhasivam CC: , , , , , , , , , , , , , , , , , , , , , References: <20240924101444.3933828-1-quic_qianyu@quicinc.com> <20240924101444.3933828-6-quic_qianyu@quicinc.com> <20240924135021.ybpyoahlpuvedma5@thinkpad> Content-Language: en-US From: Qiang Yu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nKJX1farwRB5J1ChEqRFcKmEIGJMqx-p X-Proofpoint-GUID: nKJX1farwRB5J1ChEqRFcKmEIGJMqx-p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409250026 On 9/24/2024 11:17 PM, Johan Hovold wrote: > On Tue, Sep 24, 2024 at 03:50:21PM +0200, Manivannan Sadhasivam wrote: >> On Tue, Sep 24, 2024 at 03:14:43AM -0700, Qiang Yu wrote: >>> X1E80100 has PCIe ports that support up to Gen4 x8 based on hardware IP >>> version 1.38.0. >>> >>> Currently the ops_1_9_0 which is being used for X1E80100 has config_sid >>> callback to config BDF to SID table. However, this callback is not >>> required for X1E80100 because it has smmuv3 support and BDF to SID table >>> will be not present. >>> >>> Hence add support for X1E80100 by introducing a new ops and cfg structures >>> that don't require the config_sid callback. This could be reused by the >>> future platforms based on SMMUv3. >>> >> Oops... I completely overlooked that you are not adding the SoC support but >> fixing the existing one :( Sorry for suggesting a commit message that changed >> the context. >> >> For this, you can have something like: >> >> "PCI: qcom: Fix the ops for X1E80100 SoC >> >> X1E80100 SoC is based on SMMUv3, hence it doesn't need the BDF2SID mapping >> present in the existing cfg_1_9_0 ops. This is fixed by introducing new ops >> 'ops_1_38_0' and cfg 'cfg_1_38_0' structures. These are exactly same as the >> 1_9_0 ones, but they don't have the 'config_sid()' callback that handles the >> BDF2SID mapping in the hardware. These new structures could also be used by the >> future SoCs making use of SMMUv3." > Don't we need something like this for sc8280xp and other platforms using > SMMUv3 as well? From what I know, sc8280xp and other qcom platforms are not using SMMUv3. X1E80100 and newer platforms will use SMMUv3. Thanks, Qiang > > Johan