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Thu, 24 Jul 2025 13:51:54 +0000 Message-ID: <4385ad70-f583-4ae3-ab14-cbc0cfe5129d@intel.com> Date: Thu, 24 Jul 2025 16:51:49 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 2/2] mmc: sdhci-pxav3: add state_uhs pinctrl setting To: =?UTF-8?Q?Duje_Mihanovi=C4=87?= , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Karel Balej , David Wronek , , , , , <~postmarketos/upstreaming@lists.sr.ht> References: <20250718-pxav3-uhs-v1-0-2e451256f1f6@dujemihanovic.xyz> <20250718-pxav3-uhs-v1-2-2e451256f1f6@dujemihanovic.xyz> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20250718-pxav3-uhs-v1-2-2e451256f1f6@dujemihanovic.xyz> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: DU2PR04CA0262.eurprd04.prod.outlook.com (2603:10a6:10:28e::27) To IA1PR11MB7198.namprd11.prod.outlook.com (2603:10b6:208:419::15) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|DS0PR11MB8070:EE_ X-MS-Office365-Filtering-Correlation-Id: ba968b3b-1743-421e-4813-08ddcab93f90 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|7416014|7053199007; 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> } > > +static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) > +{ > + struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); > + struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; > + > + if (clock < 100 * HZ_PER_MHZ) { > + if (!IS_ERR(pdata->pins_default)) > + pinctrl_select_state(pdata->pinctrl, pdata->pins_default); > + } else { > + if (!IS_ERR(pdata->pins_uhs)) > + pinctrl_select_state(pdata->pinctrl, pdata->pins_uhs); > + } > + > + sdhci_set_clock(host, clock); > +} > + > static const struct sdhci_ops pxav3_sdhci_ops = { > - .set_clock = sdhci_set_clock, > + .set_clock = pxav3_set_clock, > .set_power = pxav3_set_power, > .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, > .get_max_clock = sdhci_pltfm_clk_get_max_clock, > @@ -441,6 +459,16 @@ static int sdhci_pxav3_probe(struct platform_device *pdev) > host->mmc->pm_caps |= pdata->pm_caps; > } > > + pdata->pinctrl = devm_pinctrl_get(dev); > + if (IS_ERR(pdata->pinctrl)) > + dev_warn(dev, "could not get pinctrl handle\n"); > + pdata->pins_default = pinctrl_lookup_state(pdata->pinctrl, "default"); Mustn't use pdata->pinctrl if it is not valid > + if (IS_ERR(pdata->pins_default)) > + dev_warn(dev, "could not get default state\n"); > + pdata->pins_uhs = pinctrl_lookup_state(pdata->pinctrl, "state_uhs"); Mustn't use pdata->pinctrl if it is not valid, and probably don't want to change pin state unless both pdata->pins_default and pdata->pins_uhs are valid > + if (IS_ERR(pdata->pins_uhs)) > + dev_warn(dev, "could not get uhs state\n"); I'd suggest dev_dbg() rather than dev_warn() for all the new dev_warn()s > + > pm_runtime_get_noresume(&pdev->dev); > pm_runtime_set_active(&pdev->dev); > pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); > diff --git a/include/linux/platform_data/pxa_sdhci.h b/include/linux/platform_data/pxa_sdhci.h > index 899457cee425d33f82606f0b8c280003bc73d48d..540aa36db11243719707bdf22db23a8e2035674d 100644 > --- a/include/linux/platform_data/pxa_sdhci.h > +++ b/include/linux/platform_data/pxa_sdhci.h > @@ -35,6 +35,9 @@ > * @quirks: quirks of platfrom > * @quirks2: quirks2 of platfrom > * @pm_caps: pm_caps of platfrom > + * @pinctrl: pinctrl handle > + * @pins_default: default pinctrl state > + * @pins_uhs: pinctrl state for fast (>100 MHz) bus clocks > */ > struct sdhci_pxa_platdata { > unsigned int flags; > @@ -47,5 +50,9 @@ struct sdhci_pxa_platdata { > unsigned int quirks; > unsigned int quirks2; > unsigned int pm_caps; > + > + struct pinctrl *pinctrl; > + struct pinctrl_state *pins_default; > + struct pinctrl_state *pins_uhs; > }; > #endif /* _PXA_SDHCI_H_ */ >