* [PATCH 0/2] Add interconnect driver for SDX75
@ 2023-09-05 4:59 Rohit Agarwal
2023-09-05 4:59 ` [PATCH 1/2] dt-bindings: interconnect: Add compatibles " Rohit Agarwal
2023-09-05 4:59 ` [PATCH 2/2] interconnect: qcom: Add SDX75 interconnect provider driver Rohit Agarwal
0 siblings, 2 replies; 7+ messages in thread
From: Rohit Agarwal @ 2023-09-05 4:59 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, djakov, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, kernel,
Rohit Agarwal
Hi,
This series adds interconnect driver support for SDX75 platform.
Thanks,
Rohit.
Rohit Agarwal (2):
dt-bindings: interconnect: Add compatibles for SDX75
interconnect: qcom: Add SDX75 interconnect provider driver
.../bindings/interconnect/qcom,sdx75-rpmh.yaml | 100 ++
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/sdx75.c | 1134 ++++++++++++++++++++
drivers/interconnect/qcom/sdx75.h | 97 ++
include/dt-bindings/interconnect/qcom,sdx75.h | 102 ++
6 files changed, 1444 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
create mode 100644 drivers/interconnect/qcom/sdx75.c
create mode 100644 drivers/interconnect/qcom/sdx75.h
create mode 100644 include/dt-bindings/interconnect/qcom,sdx75.h
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] dt-bindings: interconnect: Add compatibles for SDX75
2023-09-05 4:59 [PATCH 0/2] Add interconnect driver for SDX75 Rohit Agarwal
@ 2023-09-05 4:59 ` Rohit Agarwal
2023-09-05 6:59 ` Krzysztof Kozlowski
2023-09-05 4:59 ` [PATCH 2/2] interconnect: qcom: Add SDX75 interconnect provider driver Rohit Agarwal
1 sibling, 1 reply; 7+ messages in thread
From: Rohit Agarwal @ 2023-09-05 4:59 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, djakov, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, kernel,
Rohit Agarwal
Add dt-bindings compatibles and interconnect IDs for
Qualcomm SDX75 platform.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
.../bindings/interconnect/qcom,sdx75-rpmh.yaml | 100 ++++++++++++++++++++
include/dt-bindings/interconnect/qcom,sdx75.h | 102 +++++++++++++++++++++
2 files changed, 202 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
create mode 100644 include/dt-bindings/interconnect/qcom,sdx75.h
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
new file mode 100644
index 0000000..f2dc87c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
+
+maintainers:
+ - Georgi Djakov <djakov@kernel.org>
+
+description:
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdx75-clk-virt
+ - qcom,sdx75-dc-noc
+ - qcom,sdx75-gem-noc
+ - qcom,sdx75-mc-virt
+ - qcom,sdx75-pcie-anoc
+ - qcom,sdx75-system-noc
+
+ '#interconnect-cells': true'
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx75-clk-virt
+ - qcom,sdx75-mc-virt
+ then:
+ properties:
+ reg: false
+ else:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx75-clk-virt
+ then:
+ properties:
+ clocks:
+ items:
+ - description: RPMH CC QPIC Clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx75-clk-virt
+ then:
+ required:
+ - clocks
+ else:
+ properties:
+ clocks: false
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,sdx75-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&rpmhcc RPMH_QPIC_CLK>;
+ };
+
+ system_noc: interconnect@1640000 {
+ compatible = "qcom,sdx75-system-noc";
+ reg = <0x1640000 0x4b400>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/include/dt-bindings/interconnect/qcom,sdx75.h b/include/dt-bindings/interconnect/qcom,sdx75.h
new file mode 100644
index 0000000..e903f5f
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sdx75.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
+
+#define MASTER_QPIC_CORE 0
+#define MASTER_QUP_CORE_0 1
+#define SLAVE_QPIC_CORE 2
+#define SLAVE_QUP_CORE_0 3
+
+#define MASTER_LLCC 0
+#define SLAVE_EBI1 1
+
+#define MASTER_CNOC_DC_NOC 0
+#define SLAVE_LAGG_CFG 1
+#define SLAVE_MCCC_MASTER 2
+#define SLAVE_GEM_NOC_CFG 3
+#define SLAVE_SNOOP_BWMON 4
+
+#define MASTER_SYS_TCU 0
+#define MASTER_APPSS_PROC 1
+#define MASTER_GEM_NOC_CFG 2
+#define MASTER_MSS_PROC 3
+#define MASTER_ANOC_PCIE_GEM_NOC 4
+#define MASTER_SNOC_SF_MEM_NOC 5
+#define MASTER_GIC 6
+#define MASTER_IPA_PCIE 7
+#define SLAVE_GEM_NOC_CNOC 8
+#define SLAVE_LLCC 9
+#define SLAVE_MEM_NOC_PCIE_SNOC 10
+#define SLAVE_SERVICE_GEM_NOC 11
+
+#define MASTER_PCIE_0 0
+#define MASTER_PCIE_1 1
+#define MASTER_PCIE_2 2
+#define SLAVE_ANOC_PCIE_GEM_NOC 3
+
+#define MASTER_AUDIO 0
+#define MASTER_GIC_AHB 1
+#define MASTER_PCIE_RSCC 2
+#define MASTER_QDSS_BAM 3
+#define MASTER_QPIC 4
+#define MASTER_QUP_0 5
+#define MASTER_ANOC_SNOC 6
+#define MASTER_GEM_NOC_CNOC 7
+#define MASTER_GEM_NOC_PCIE_SNOC 8
+#define MASTER_SNOC_CFG 9
+#define MASTER_PCIE_ANOC_CFG 10
+#define MASTER_CRYPTO 11
+#define MASTER_IPA 12
+#define MASTER_MVMSS 13
+#define MASTER_EMAC_0 14
+#define MASTER_EMAC_1 15
+#define MASTER_QDSS_ETR 16
+#define MASTER_QDSS_ETR_1 17
+#define MASTER_SDCC_1 18
+#define MASTER_SDCC_4 19
+#define MASTER_USB3_0 20
+#define SLAVE_ETH0_CFG 21
+#define SLAVE_ETH1_CFG 22
+#define SLAVE_AUDIO 23
+#define SLAVE_CLK_CTL 24
+#define SLAVE_CRYPTO_0_CFG 25
+#define SLAVE_IMEM_CFG 26
+#define SLAVE_IPA_CFG 27
+#define SLAVE_IPC_ROUTER_CFG 28
+#define SLAVE_CNOC_MSS 29
+#define SLAVE_ICBDI_MVMSS_CFG 30
+#define SLAVE_PCIE_0_CFG 31
+#define SLAVE_PCIE_1_CFG 32
+#define SLAVE_PCIE_2_CFG 33
+#define SLAVE_PCIE_RSC_CFG 34
+#define SLAVE_PDM 35
+#define SLAVE_PRNG 36
+#define SLAVE_QDSS_CFG 37
+#define SLAVE_QPIC 38
+#define SLAVE_QUP_0 39
+#define SLAVE_SDCC_1 40
+#define SLAVE_SDCC_4 41
+#define SLAVE_SPMI_VGI_COEX 42
+#define SLAVE_TCSR 43
+#define SLAVE_TLMM 44
+#define SLAVE_USB3 45
+#define SLAVE_USB3_PHY_CFG 46
+#define SLAVE_A1NOC_CFG 47
+#define SLAVE_DDRSS_CFG 48
+#define SLAVE_SNOC_GEM_NOC_SF 49
+#define SLAVE_SNOC_CFG 50
+#define SLAVE_PCIE_ANOC_CFG 51
+#define SLAVE_IMEM 52
+#define SLAVE_SERVICE_PCIE_ANOC 53
+#define SLAVE_SERVICE_SNOC 54
+#define SLAVE_PCIE_0 55
+#define SLAVE_PCIE_1 56
+#define SLAVE_PCIE_2 57
+#define SLAVE_QDSS_STM 58
+#define SLAVE_TCU 59
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] interconnect: qcom: Add SDX75 interconnect provider driver
2023-09-05 4:59 [PATCH 0/2] Add interconnect driver for SDX75 Rohit Agarwal
2023-09-05 4:59 ` [PATCH 1/2] dt-bindings: interconnect: Add compatibles " Rohit Agarwal
@ 2023-09-05 4:59 ` Rohit Agarwal
2023-09-05 7:02 ` Krzysztof Kozlowski
1 sibling, 1 reply; 7+ messages in thread
From: Rohit Agarwal @ 2023-09-05 4:59 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, djakov, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, kernel,
Rohit Agarwal
Add driver for the Qualcomm interconnect buses found in SDX75.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/sdx75.c | 1134 ++++++++++++++++++++++++++++++++++++
drivers/interconnect/qcom/sdx75.h | 97 +++
4 files changed, 1242 insertions(+)
create mode 100644 drivers/interconnect/qcom/sdx75.c
create mode 100644 drivers/interconnect/qcom/sdx75.h
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 825b647..62b516d 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -182,6 +182,15 @@ config INTERCONNECT_QCOM_SDX65
This is a driver for the Qualcomm Network-on-Chip on sdx65-based
platforms.
+config INTERCONNECT_QCOM_SDX75
+ tristate "Qualcomm SDX75 interconnect driver"
+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ help
+ This is a driver for the Qualcomm Network-on-Chip on sdx75-based
+ platforms.
+
config INTERCONNECT_QCOM_SM6350
tristate "Qualcomm SM6350 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index ab98892..55cd503 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -23,6 +23,7 @@ qnoc-sdm670-objs := sdm670.o
qnoc-sdm845-objs := sdm845.o
qnoc-sdx55-objs := sdx55.o
qnoc-sdx65-objs := sdx65.o
+qnoc-sdx75-objs := sdx75.o
qnoc-sm6350-objs := sm6350.o
qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
@@ -51,6 +52,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
+obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c
new file mode 100644
index 0000000..4a2ab0c
--- /dev/null
+++ b/drivers/interconnect/qcom/sdx75.c
@@ -0,0 +1,1134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,sdx75.h>
+
+#include "bcm-voter.h"
+#include "icc-common.h"
+#include "icc-rpmh.h"
+#include "sdx75.h"
+
+static struct qcom_icc_node qpic_core_master = {
+ .name = "qpic_core_master",
+ .id = SDX75_MASTER_QPIC_CORE,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_QPIC_CORE },
+};
+
+static struct qcom_icc_node qup0_core_master = {
+ .name = "qup0_core_master",
+ .id = SDX75_MASTER_QUP_CORE_0,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_QUP_CORE_0 },
+};
+
+static struct qcom_icc_node qnm_cnoc = {
+ .name = "qnm_cnoc",
+ .id = SDX75_MASTER_CNOC_DC_NOC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 4,
+ .links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER,
+ SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON },
+};
+
+static struct qcom_icc_node alm_sys_tcu = {
+ .name = "alm_sys_tcu",
+ .id = SDX75_MASTER_SYS_TCU,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 2,
+ .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
+};
+
+static struct qcom_icc_node chm_apps = {
+ .name = "chm_apps",
+ .id = SDX75_MASTER_APPSS_PROC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
+ SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cfg = {
+ .name = "qnm_gemnoc_cfg",
+ .id = SDX75_MASTER_GEM_NOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_SERVICE_GEM_NOC },
+};
+
+static struct qcom_icc_node qnm_mdsp = {
+ .name = "qnm_mdsp",
+ .id = SDX75_MASTER_MSS_PROC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
+ SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+};
+
+static struct qcom_icc_node qnm_pcie = {
+ .name = "qnm_pcie",
+ .id = SDX75_MASTER_ANOC_PCIE_GEM_NOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 2,
+ .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC },
+};
+
+static struct qcom_icc_node qnm_snoc_sf = {
+ .name = "qnm_snoc_sf",
+ .id = SDX75_MASTER_SNOC_SF_MEM_NOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC,
+ SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+};
+
+static struct qcom_icc_node xm_gic = {
+ .name = "xm_gic",
+ .id = SDX75_MASTER_GIC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_LLCC },
+};
+
+static struct qcom_icc_node xm_ipa2pcie = {
+ .name = "xm_ipa2pcie",
+ .id = SDX75_MASTER_IPA_PCIE,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC },
+};
+
+static struct qcom_icc_node llcc_mc = {
+ .name = "llcc_mc",
+ .id = SDX75_MASTER_LLCC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_EBI1 },
+};
+
+static struct qcom_icc_node xm_pcie3_0 = {
+ .name = "xm_pcie3_0",
+ .id = SDX75_MASTER_PCIE_0,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
+};
+
+static struct qcom_icc_node xm_pcie3_1 = {
+ .name = "xm_pcie3_1",
+ .id = SDX75_MASTER_PCIE_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
+};
+
+static struct qcom_icc_node xm_pcie3_2 = {
+ .name = "xm_pcie3_2",
+ .id = SDX75_MASTER_PCIE_2,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC },
+};
+
+static struct qcom_icc_node qhm_audio = {
+ .name = "qhm_audio",
+ .id = SDX75_MASTER_AUDIO,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qhm_gic = {
+ .name = "qhm_gic",
+ .id = SDX75_MASTER_GIC_AHB,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qhm_pcie_rscc = {
+ .name = "qhm_pcie_rscc",
+ .id = SDX75_MASTER_PCIE_RSCC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 31,
+ .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
+ SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
+ SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
+ SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
+ SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
+ SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
+ SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM,
+ SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG,
+ SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0,
+ SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4,
+ SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR,
+ SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3,
+ SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG,
+ SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG,
+ SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM,
+ SDX75_SLAVE_TCU },
+};
+
+static struct qcom_icc_node qhm_qdss_bam = {
+ .name = "qhm_qdss_bam",
+ .id = SDX75_MASTER_QDSS_BAM,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node qhm_qpic = {
+ .name = "qhm_qpic",
+ .id = SDX75_MASTER_QPIC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node qhm_qup0 = {
+ .name = "qhm_qup0",
+ .id = SDX75_MASTER_QUP_0,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node qnm_aggre_noc = {
+ .name = "qnm_aggre_noc",
+ .id = SDX75_MASTER_ANOC_SNOC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cnoc = {
+ .name = "qnm_gemnoc_cnoc",
+ .id = SDX75_MASTER_GEM_NOC_CNOC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 32,
+ .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG,
+ SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL,
+ SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG,
+ SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG,
+ SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG,
+ SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG,
+ SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG,
+ SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG,
+ SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC,
+ SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1,
+ SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX,
+ SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM,
+ SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG,
+ SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG,
+ SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM,
+ SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU },
+};
+
+static struct qcom_icc_node qnm_gemnoc_pcie = {
+ .name = "qnm_gemnoc_pcie",
+ .id = SDX75_MASTER_GEM_NOC_PCIE_SNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1,
+ SDX75_SLAVE_PCIE_2 },
+};
+
+static struct qcom_icc_node qnm_system_noc_cfg = {
+ .name = "qnm_system_noc_cfg",
+ .id = SDX75_MASTER_SNOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_SERVICE_SNOC },
+};
+
+static struct qcom_icc_node qnm_system_noc_pcie_cfg = {
+ .name = "qnm_system_noc_pcie_cfg",
+ .id = SDX75_MASTER_PCIE_ANOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_SERVICE_PCIE_ANOC },
+};
+
+static struct qcom_icc_node qxm_crypto = {
+ .name = "qxm_crypto",
+ .id = SDX75_MASTER_CRYPTO,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node qxm_ipa = {
+ .name = "qxm_ipa",
+ .id = SDX75_MASTER_IPA,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qxm_mvmss = {
+ .name = "qxm_mvmss",
+ .id = SDX75_MASTER_MVMSS,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node xm_emac_0 = {
+ .name = "xm_emac_0",
+ .id = SDX75_MASTER_EMAC_0,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node xm_emac_1 = {
+ .name = "xm_emac_1",
+ .id = SDX75_MASTER_EMAC_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node xm_qdss_etr0 = {
+ .name = "xm_qdss_etr0",
+ .id = SDX75_MASTER_QDSS_ETR,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node xm_qdss_etr1 = {
+ .name = "xm_qdss_etr1",
+ .id = SDX75_MASTER_QDSS_ETR_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node xm_sdc1 = {
+ .name = "xm_sdc1",
+ .id = SDX75_MASTER_SDCC_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node xm_sdc4 = {
+ .name = "xm_sdc4",
+ .id = SDX75_MASTER_SDCC_4,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node xm_usb3 = {
+ .name = "xm_usb3",
+ .id = SDX75_MASTER_USB3_0,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_SLAVE_A1NOC_CFG },
+};
+
+static struct qcom_icc_node qpic_core_slave = {
+ .name = "qpic_core_slave",
+ .id = SDX75_SLAVE_QPIC_CORE,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qup0_core_slave = {
+ .name = "qup0_core_slave",
+ .id = SDX75_SLAVE_QUP_CORE_0,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_lagg = {
+ .name = "qhs_lagg",
+ .id = SDX75_SLAVE_LAGG_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_mccc_master = {
+ .name = "qhs_mccc_master",
+ .id = SDX75_SLAVE_MCCC_MASTER,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qns_gemnoc = {
+ .name = "qns_gemnoc",
+ .id = SDX75_SLAVE_GEM_NOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qss_snoop_bwmon = {
+ .name = "qss_snoop_bwmon",
+ .id = SDX75_SLAVE_SNOOP_BWMON,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qns_gemnoc_cnoc = {
+ .name = "qns_gemnoc_cnoc",
+ .id = SDX75_SLAVE_GEM_NOC_CNOC,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_MASTER_GEM_NOC_CNOC },
+};
+
+static struct qcom_icc_node qns_llcc = {
+ .name = "qns_llcc",
+ .id = SDX75_SLAVE_LLCC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { SDX75_MASTER_LLCC },
+};
+
+static struct qcom_icc_node qns_pcie = {
+ .name = "qns_pcie",
+ .id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC },
+};
+
+static struct qcom_icc_node srvc_gemnoc = {
+ .name = "srvc_gemnoc",
+ .id = SDX75_SLAVE_SERVICE_GEM_NOC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node ebi = {
+ .name = "ebi",
+ .id = SDX75_SLAVE_EBI1,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qns_pcie_gemnoc = {
+ .name = "qns_pcie_gemnoc",
+ .id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC },
+};
+
+static struct qcom_icc_node ps_eth0_cfg = {
+ .name = "ps_eth0_cfg",
+ .id = SDX75_SLAVE_ETH0_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node ps_eth1_cfg = {
+ .name = "ps_eth1_cfg",
+ .id = SDX75_SLAVE_ETH1_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_audio = {
+ .name = "qhs_audio",
+ .id = SDX75_SLAVE_AUDIO,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_clk_ctl = {
+ .name = "qhs_clk_ctl",
+ .id = SDX75_SLAVE_CLK_CTL,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_crypto_cfg = {
+ .name = "qhs_crypto_cfg",
+ .id = SDX75_SLAVE_CRYPTO_0_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_imem_cfg = {
+ .name = "qhs_imem_cfg",
+ .id = SDX75_SLAVE_IMEM_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_ipa = {
+ .name = "qhs_ipa",
+ .id = SDX75_SLAVE_IPA_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_ipc_router = {
+ .name = "qhs_ipc_router",
+ .id = SDX75_SLAVE_IPC_ROUTER_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_mss_cfg = {
+ .name = "qhs_mss_cfg",
+ .id = SDX75_SLAVE_CNOC_MSS,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_mvmss_cfg = {
+ .name = "qhs_mvmss_cfg",
+ .id = SDX75_SLAVE_ICBDI_MVMSS_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_pcie0_cfg = {
+ .name = "qhs_pcie0_cfg",
+ .id = SDX75_SLAVE_PCIE_0_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_pcie1_cfg = {
+ .name = "qhs_pcie1_cfg",
+ .id = SDX75_SLAVE_PCIE_1_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_pcie2_cfg = {
+ .name = "qhs_pcie2_cfg",
+ .id = SDX75_SLAVE_PCIE_2_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_pcie_rscc = {
+ .name = "qhs_pcie_rscc",
+ .id = SDX75_SLAVE_PCIE_RSC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_pdm = {
+ .name = "qhs_pdm",
+ .id = SDX75_SLAVE_PDM,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_prng = {
+ .name = "qhs_prng",
+ .id = SDX75_SLAVE_PRNG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_qdss_cfg = {
+ .name = "qhs_qdss_cfg",
+ .id = SDX75_SLAVE_QDSS_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_qpic = {
+ .name = "qhs_qpic",
+ .id = SDX75_SLAVE_QPIC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_qup0 = {
+ .name = "qhs_qup0",
+ .id = SDX75_SLAVE_QUP_0,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_sdc1 = {
+ .name = "qhs_sdc1",
+ .id = SDX75_SLAVE_SDCC_1,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_sdc4 = {
+ .name = "qhs_sdc4",
+ .id = SDX75_SLAVE_SDCC_4,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_spmi_vgi_coex = {
+ .name = "qhs_spmi_vgi_coex",
+ .id = SDX75_SLAVE_SPMI_VGI_COEX,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_tcsr = {
+ .name = "qhs_tcsr",
+ .id = SDX75_SLAVE_TCSR,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_tlmm = {
+ .name = "qhs_tlmm",
+ .id = SDX75_SLAVE_TLMM,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_usb3 = {
+ .name = "qhs_usb3",
+ .id = SDX75_SLAVE_USB3,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qhs_usb3_phy = {
+ .name = "qhs_usb3_phy",
+ .id = SDX75_SLAVE_USB3_PHY_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node qns_a1noc = {
+ .name = "qns_a1noc",
+ .id = SDX75_SLAVE_A1NOC_CFG,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .links = { SDX75_MASTER_ANOC_SNOC },
+};
+
+static struct qcom_icc_node qns_ddrss_cfg = {
+ .name = "qns_ddrss_cfg",
+ .id = SDX75_SLAVE_DDRSS_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_MASTER_CNOC_DC_NOC },
+};
+
+static struct qcom_icc_node qns_gemnoc_sf = {
+ .name = "qns_gemnoc_sf",
+ .id = SDX75_SLAVE_SNOC_GEM_NOC_SF,
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .links = { SDX75_MASTER_SNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qns_system_noc_cfg = {
+ .name = "qns_system_noc_cfg",
+ .id = SDX75_SLAVE_SNOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_MASTER_SNOC_CFG },
+};
+
+static struct qcom_icc_node qns_system_noc_pcie_cfg = {
+ .name = "qns_system_noc_pcie_cfg",
+ .id = SDX75_SLAVE_PCIE_ANOC_CFG,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SDX75_MASTER_PCIE_ANOC_CFG },
+};
+
+static struct qcom_icc_node qxs_imem = {
+ .name = "qxs_imem",
+ .id = SDX75_SLAVE_IMEM,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node srvc_pcie_system_noc = {
+ .name = "srvc_pcie_system_noc",
+ .id = SDX75_SLAVE_SERVICE_PCIE_ANOC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node srvc_system_noc = {
+ .name = "srvc_system_noc",
+ .id = SDX75_SLAVE_SERVICE_SNOC,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node xs_pcie_0 = {
+ .name = "xs_pcie_0",
+ .id = SDX75_SLAVE_PCIE_0,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node xs_pcie_1 = {
+ .name = "xs_pcie_1",
+ .id = SDX75_SLAVE_PCIE_1,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node xs_pcie_2 = {
+ .name = "xs_pcie_2",
+ .id = SDX75_SLAVE_PCIE_2,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node xs_qdss_stm = {
+ .name = "xs_qdss_stm",
+ .id = SDX75_SLAVE_QDSS_STM,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 0,
+};
+
+static struct qcom_icc_node xs_sys_tcu_cfg = {
+ .name = "xs_sys_tcu_cfg",
+ .id = SDX75_SLAVE_TCU,
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 0,
+};
+
+static struct qcom_icc_bcm bcm_ce0 = {
+ .name = "CE0",
+ .num_nodes = 1,
+ .nodes = { &qxm_crypto },
+};
+
+static struct qcom_icc_bcm bcm_cn0 = {
+ .name = "CN0",
+ .keepalive = true,
+ .num_nodes = 39,
+ .nodes = { &qhm_pcie_rscc, &qnm_gemnoc_cnoc,
+ &ps_eth0_cfg, &ps_eth1_cfg,
+ &qhs_audio, &qhs_clk_ctl,
+ &qhs_crypto_cfg, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_mss_cfg, &qhs_mvmss_cfg,
+ &qhs_pcie0_cfg, &qhs_pcie1_cfg,
+ &qhs_pcie2_cfg, &qhs_pcie_rscc,
+ &qhs_pdm, &qhs_prng,
+ &qhs_qdss_cfg, &qhs_qpic,
+ &qhs_qup0, &qhs_sdc1,
+ &qhs_sdc4, &qhs_spmi_vgi_coex,
+ &qhs_tcsr, &qhs_tlmm,
+ &qhs_usb3, &qhs_usb3_phy,
+ &qns_ddrss_cfg, &qns_system_noc_cfg,
+ &qns_system_noc_pcie_cfg, &qxs_imem,
+ &srvc_pcie_system_noc, &srvc_system_noc,
+ &xs_pcie_0, &xs_pcie_1,
+ &xs_pcie_2, &xs_qdss_stm,
+ &xs_sys_tcu_cfg },
+};
+
+static struct qcom_icc_bcm bcm_mc0 = {
+ .name = "MC0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_qp0 = {
+ .name = "QP0",
+ .num_nodes = 1,
+ .nodes = { &qpic_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup0 = {
+ .name = "QUP0",
+ .keepalive = true,
+ .vote_scale = 1,
+ .num_nodes = 1,
+ .nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_sh0 = {
+ .name = "SH0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_bcm bcm_sh1 = {
+ .name = "SH1",
+ .num_nodes = 10,
+ .nodes = { &alm_sys_tcu, &chm_apps,
+ &qnm_gemnoc_cfg, &qnm_mdsp,
+ &qnm_snoc_sf, &xm_gic,
+ &xm_ipa2pcie, &qns_gemnoc_cnoc,
+ &qns_pcie, &srvc_gemnoc },
+};
+
+static struct qcom_icc_bcm bcm_sn0 = {
+ .name = "SN0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_bcm bcm_sn1 = {
+ .name = "SN1",
+ .num_nodes = 21,
+ .nodes = { &xm_pcie3_0, &xm_pcie3_1,
+ &xm_pcie3_2, &qhm_audio,
+ &qhm_gic, &qhm_qdss_bam,
+ &qhm_qpic, &qhm_qup0,
+ &qnm_gemnoc_pcie, &qnm_system_noc_cfg,
+ &qnm_system_noc_pcie_cfg, &qxm_crypto,
+ &qxm_ipa, &qxm_mvmss,
+ &xm_emac_0, &xm_emac_1,
+ &xm_qdss_etr0, &xm_qdss_etr1,
+ &xm_sdc1, &xm_sdc4,
+ &xm_usb3 },
+};
+
+static struct qcom_icc_bcm bcm_sn2 = {
+ .name = "SN2",
+ .num_nodes = 2,
+ .nodes = { &qnm_aggre_noc, &qns_a1noc },
+};
+
+static struct qcom_icc_bcm bcm_sn4 = {
+ .name = "SN4",
+ .num_nodes = 2,
+ .nodes = { &qnm_pcie, &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_bcm *clk_virt_bcms[] = {
+ &bcm_qp0,
+ &bcm_qup0,
+};
+
+static struct qcom_icc_node *clk_virt_nodes[] = {
+ [MASTER_QPIC_CORE] = &qpic_core_master,
+ [MASTER_QUP_CORE_0] = &qup0_core_master,
+ [SLAVE_QPIC_CORE] = &qpic_core_slave,
+ [SLAVE_QUP_CORE_0] = &qup0_core_slave,
+};
+
+static struct qcom_icc_desc sdx75_clk_virt = {
+ .nodes = clk_virt_nodes,
+ .num_nodes = ARRAY_SIZE(clk_virt_nodes),
+ .bcms = clk_virt_bcms,
+ .num_bcms = ARRAY_SIZE(clk_virt_bcms),
+};
+
+static struct qcom_icc_bcm *dc_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *dc_noc_nodes[] = {
+ [MASTER_CNOC_DC_NOC] = &qnm_cnoc,
+ [SLAVE_LAGG_CFG] = &qhs_lagg,
+ [SLAVE_MCCC_MASTER] = &qhs_mccc_master,
+ [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
+ [SLAVE_SNOOP_BWMON] = &qss_snoop_bwmon,
+};
+
+static struct qcom_icc_desc sdx75_dc_noc = {
+ .nodes = dc_noc_nodes,
+ .num_nodes = ARRAY_SIZE(dc_noc_nodes),
+ .bcms = dc_noc_bcms,
+ .num_bcms = ARRAY_SIZE(dc_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gem_noc_bcms[] = {
+ &bcm_sh0,
+ &bcm_sh1,
+ &bcm_sn4,
+};
+
+static struct qcom_icc_node *gem_noc_nodes[] = {
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_APPSS_PROC] = &chm_apps,
+ [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
+ [MASTER_MSS_PROC] = &qnm_mdsp,
+ [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [MASTER_GIC] = &xm_gic,
+ [MASTER_IPA_PCIE] = &xm_ipa2pcie,
+ [SLAVE_GEM_NOC_CNOC] = &qns_gemnoc_cnoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
+ [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
+};
+
+static struct qcom_icc_desc sdx75_gem_noc = {
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm *mc_virt_bcms[] = {
+ &bcm_mc0,
+};
+
+static struct qcom_icc_node *mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [SLAVE_EBI1] = &ebi,
+};
+
+static struct qcom_icc_desc sdx75_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
+ &bcm_sn1,
+ &bcm_sn4,
+};
+
+static struct qcom_icc_node *pcie_anoc_nodes[] = {
+ [MASTER_PCIE_0] = &xm_pcie3_0,
+ [MASTER_PCIE_1] = &xm_pcie3_1,
+ [MASTER_PCIE_2] = &xm_pcie3_2,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
+};
+
+static struct qcom_icc_desc sdx75_pcie_anoc = {
+ .nodes = pcie_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
+ .bcms = pcie_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
+};
+
+static struct qcom_icc_bcm *system_noc_bcms[] = {
+ &bcm_ce0,
+ &bcm_cn0,
+ &bcm_sn0,
+ &bcm_sn1,
+ &bcm_sn2,
+};
+
+static struct qcom_icc_node *system_noc_nodes[] = {
+ [MASTER_AUDIO] = &qhm_audio,
+ [MASTER_GIC_AHB] = &qhm_gic,
+ [MASTER_PCIE_RSCC] = &qhm_pcie_rscc,
+ [MASTER_QDSS_BAM] = &qhm_qdss_bam,
+ [MASTER_QPIC] = &qhm_qpic,
+ [MASTER_QUP_0] = &qhm_qup0,
+ [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
+ [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+ [MASTER_SNOC_CFG] = &qnm_system_noc_cfg,
+ [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg,
+ [MASTER_CRYPTO] = &qxm_crypto,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_MVMSS] = &qxm_mvmss,
+ [MASTER_EMAC_0] = &xm_emac_0,
+ [MASTER_EMAC_1] = &xm_emac_1,
+ [MASTER_QDSS_ETR] = &xm_qdss_etr0,
+ [MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
+ [MASTER_SDCC_1] = &xm_sdc1,
+ [MASTER_SDCC_4] = &xm_sdc4,
+ [MASTER_USB3_0] = &xm_usb3,
+ [SLAVE_ETH0_CFG] = &ps_eth0_cfg,
+ [SLAVE_ETH1_CFG] = &ps_eth1_cfg,
+ [SLAVE_AUDIO] = &qhs_audio,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+ [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
+ [SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
+ [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
+ [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc,
+ [SLAVE_PDM] = &qhs_pdm,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
+ [SLAVE_QPIC] = &qhs_qpic,
+ [SLAVE_QUP_0] = &qhs_qup0,
+ [SLAVE_SDCC_1] = &qhs_sdc1,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
+ [SLAVE_TCSR] = &qhs_tcsr,
+ [SLAVE_TLMM] = &qhs_tlmm,
+ [SLAVE_USB3] = &qhs_usb3,
+ [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
+ [SLAVE_A1NOC_CFG] = &qns_a1noc,
+ [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+ [SLAVE_SNOC_CFG] = &qns_system_noc_cfg,
+ [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg,
+ [SLAVE_IMEM] = &qxs_imem,
+ [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc,
+ [SLAVE_SERVICE_SNOC] = &srvc_system_noc,
+ [SLAVE_PCIE_0] = &xs_pcie_0,
+ [SLAVE_PCIE_1] = &xs_pcie_1,
+ [SLAVE_PCIE_2] = &xs_pcie_2,
+ [SLAVE_QDSS_STM] = &xs_qdss_stm,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static struct qcom_icc_desc sdx75_system_noc = {
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static int qnoc_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = qcom_icc_rpmh_probe(pdev);
+ if (ret)
+ dev_err(&pdev->dev, "failed to register ICC provider\n");
+
+ return ret;
+}
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,sdx75-clk-virt",
+ .data = &sdx75_clk_virt
+ },
+ { .compatible = "qcom,sdx75-dc-noc",
+ .data = &sdx75_dc_noc
+ },
+ { .compatible = "qcom,sdx75-gem-noc",
+ .data = &sdx75_gem_noc
+ },
+ { .compatible = "qcom,sdx75-mc-virt",
+ .data = &sdx75_mc_virt
+ },
+ { .compatible = "qcom,sdx75-pcie-anoc",
+ .data = &sdx75_pcie_anoc
+ },
+ { .compatible = "qcom,sdx75-system-noc",
+ .data = &sdx75_system_noc
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qnoc_probe,
+ .remove = qcom_icc_rpmh_remove,
+ .driver = {
+ .name = "qnoc-sdx75",
+ .of_match_table = qnoc_of_match,
+ .sync_state = icc_sync_state,
+ },
+};
+
+static int __init qnoc_driver_init(void)
+{
+ return platform_driver_register(&qnoc_driver);
+}
+core_initcall(qnoc_driver_init);
+
+static void __exit qnoc_driver_exit(void)
+{
+ platform_driver_unregister(&qnoc_driver);
+}
+
+MODULE_DESCRIPTION("SDX75 NoC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h
new file mode 100644
index 0000000..24e8871
--- /dev/null
+++ b/drivers/interconnect/qcom/sdx75.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H
+#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H
+
+#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0
+#define SDX75_MASTER_ANOC_SNOC 1
+#define SDX75_MASTER_APPSS_PROC 2
+#define SDX75_MASTER_AUDIO 3
+#define SDX75_MASTER_CNOC_DC_NOC 4
+#define SDX75_MASTER_CRYPTO 5
+#define SDX75_MASTER_EMAC_0 6
+#define SDX75_MASTER_EMAC_1 7
+#define SDX75_MASTER_GEM_NOC_CFG 8
+#define SDX75_MASTER_GEM_NOC_CNOC 9
+#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10
+#define SDX75_MASTER_GIC 11
+#define SDX75_MASTER_GIC_AHB 12
+#define SDX75_MASTER_IPA 13
+#define SDX75_MASTER_IPA_PCIE 14
+#define SDX75_MASTER_LLCC 15
+#define SDX75_MASTER_MSS_PROC 16
+#define SDX75_MASTER_MVMSS 17
+#define SDX75_MASTER_PCIE_0 18
+#define SDX75_MASTER_PCIE_1 19
+#define SDX75_MASTER_PCIE_2 20
+#define SDX75_MASTER_PCIE_ANOC_CFG 21
+#define SDX75_MASTER_PCIE_RSCC 22
+#define SDX75_MASTER_QDSS_BAM 23
+#define SDX75_MASTER_QDSS_ETR 24
+#define SDX75_MASTER_QDSS_ETR_1 25
+#define SDX75_MASTER_QPIC 26
+#define SDX75_MASTER_QPIC_CORE 27
+#define SDX75_MASTER_QUP_0 28
+#define SDX75_MASTER_QUP_CORE_0 29
+#define SDX75_MASTER_SDCC_1 30
+#define SDX75_MASTER_SDCC_4 31
+#define SDX75_MASTER_SNOC_CFG 32
+#define SDX75_MASTER_SNOC_SF_MEM_NOC 33
+#define SDX75_MASTER_SYS_TCU 34
+#define SDX75_MASTER_USB3_0 35
+#define SDX75_SLAVE_A1NOC_CFG 36
+#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37
+#define SDX75_SLAVE_AUDIO 38
+#define SDX75_SLAVE_CLK_CTL 39
+#define SDX75_SLAVE_CRYPTO_0_CFG 40
+#define SDX75_SLAVE_CNOC_MSS 41
+#define SDX75_SLAVE_DDRSS_CFG 42
+#define SDX75_SLAVE_EBI1 43
+#define SDX75_SLAVE_ETH0_CFG 44
+#define SDX75_SLAVE_ETH1_CFG 45
+#define SDX75_SLAVE_GEM_NOC_CFG 46
+#define SDX75_SLAVE_GEM_NOC_CNOC 47
+#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48
+#define SDX75_SLAVE_IMEM 49
+#define SDX75_SLAVE_IMEM_CFG 50
+#define SDX75_SLAVE_IPA_CFG 51
+#define SDX75_SLAVE_IPC_ROUTER_CFG 52
+#define SDX75_SLAVE_LAGG_CFG 53
+#define SDX75_SLAVE_LLCC 54
+#define SDX75_SLAVE_MCCC_MASTER 55
+#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56
+#define SDX75_SLAVE_PCIE_0 57
+#define SDX75_SLAVE_PCIE_1 58
+#define SDX75_SLAVE_PCIE_2 59
+#define SDX75_SLAVE_PCIE_0_CFG 60
+#define SDX75_SLAVE_PCIE_1_CFG 61
+#define SDX75_SLAVE_PCIE_2_CFG 62
+#define SDX75_SLAVE_PCIE_ANOC_CFG 63
+#define SDX75_SLAVE_PCIE_RSC_CFG 64
+#define SDX75_SLAVE_PDM 65
+#define SDX75_SLAVE_PRNG 66
+#define SDX75_SLAVE_QDSS_CFG 67
+#define SDX75_SLAVE_QDSS_STM 68
+#define SDX75_SLAVE_QPIC 69
+#define SDX75_SLAVE_QPIC_CORE 70
+#define SDX75_SLAVE_QUP_0 71
+#define SDX75_SLAVE_QUP_CORE_0 72
+#define SDX75_SLAVE_SDCC_1 73
+#define SDX75_SLAVE_SDCC_4 74
+#define SDX75_SLAVE_SERVICE_GEM_NOC 75
+#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76
+#define SDX75_SLAVE_SERVICE_SNOC 77
+#define SDX75_SLAVE_SNOC_CFG 78
+#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79
+#define SDX75_SLAVE_SNOOP_BWMON 80
+#define SDX75_SLAVE_SPMI_VGI_COEX 81
+#define SDX75_SLAVE_TCSR 82
+#define SDX75_SLAVE_TCU 83
+#define SDX75_SLAVE_TLMM 84
+#define SDX75_SLAVE_USB3 85
+#define SDX75_SLAVE_USB3_PHY_CFG 86
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings: interconnect: Add compatibles for SDX75
2023-09-05 4:59 ` [PATCH 1/2] dt-bindings: interconnect: Add compatibles " Rohit Agarwal
@ 2023-09-05 6:59 ` Krzysztof Kozlowski
2023-09-05 7:14 ` Rohit Agarwal
0 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-05 6:59 UTC (permalink / raw)
To: Rohit Agarwal, agross, andersson, konrad.dybcio, djakov, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, kernel
On 05/09/2023 06:59, Rohit Agarwal wrote:
> Add dt-bindings compatibles and interconnect IDs for
> Qualcomm SDX75 platform.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
> .../bindings/interconnect/qcom,sdx75-rpmh.yaml | 100 ++++++++++++++++++++
> include/dt-bindings/interconnect/qcom,sdx75.h | 102 +++++++++++++++++++++
> 2 files changed, 202 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
> create mode 100644 include/dt-bindings/interconnect/qcom,sdx75.h
>
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
> new file mode 100644
> index 0000000..f2dc87c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
> +
> +maintainers:
> + - Georgi Djakov <djakov@kernel.org>
I don't think Georgi maintains this device. It's maintainer of device,
not the subsystem.
> +
> +description:
> + RPMh interconnect providers support system bandwidth requirements through
> + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
> + able to communicate with the BCM through the Resource State Coordinator (RSC)
> + associated with each execution environment. Provider nodes must point to at
> + least one RPMh device child node pertaining to their RSC and each provider
> + can map to multiple RPMh resources.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sdx75-clk-virt
> + - qcom,sdx75-dc-noc
> + - qcom,sdx75-gem-noc
> + - qcom,sdx75-mc-virt
> + - qcom,sdx75-pcie-anoc
> + - qcom,sdx75-system-noc
> +
> + '#interconnect-cells': true'
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> +allOf:
> + - $ref: qcom,rpmh-common.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdx75-clk-virt
> + - qcom,sdx75-mc-virt
> + then:
> + properties:
> + reg: false
> + else:
> + required:
> + - reg
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdx75-clk-virt
> + then:
> + properties:
> + clocks:
> + items:
> + - description: RPMH CC QPIC Clock
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sdx75-clk-virt
This if: clause should be merged with the one earlier.
> + then:
> + required:
> + - clocks
> + else:
> + properties:
> + clocks: false
> +
> +required:
> + - compatible
Please keep the order like in example-schema, so required: goes before
allOf.
> +
> +unevaluatedProperties: false
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] interconnect: qcom: Add SDX75 interconnect provider driver
2023-09-05 4:59 ` [PATCH 2/2] interconnect: qcom: Add SDX75 interconnect provider driver Rohit Agarwal
@ 2023-09-05 7:02 ` Krzysztof Kozlowski
2023-09-05 7:20 ` Rohit Agarwal
0 siblings, 1 reply; 7+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-05 7:02 UTC (permalink / raw)
To: Rohit Agarwal, agross, andersson, konrad.dybcio, djakov, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, kernel
On 05/09/2023 06:59, Rohit Agarwal wrote:
> Add driver for the Qualcomm interconnect buses found in SDX75.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
...
> +
> +static struct qcom_icc_bcm *system_noc_bcms[] = {
Please do not copy your code from downstream, but work on upstream. We
changed this long time ago, so you clearly used some old or obsolete
file as template.
> + &bcm_ce0,
> + &bcm_cn0,
> + &bcm_sn0,
> + &bcm_sn1,
> + &bcm_sn2,
> +};
> +
> +static struct qcom_icc_node *system_noc_nodes[] = {
> + [MASTER_AUDIO] = &qhm_audio,
> + [MASTER_GIC_AHB] = &qhm_gic,
> + [MASTER_PCIE_RSCC] = &qhm_pcie_rscc,
> + [MASTER_QDSS_BAM] = &qhm_qdss_bam,
> + [MASTER_QPIC] = &qhm_qpic,
> + [MASTER_QUP_0] = &qhm_qup0,
> + [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
> + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
> + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
> + [MASTER_SNOC_CFG] = &qnm_system_noc_cfg,
> + [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg,
> + [MASTER_CRYPTO] = &qxm_crypto,
> + [MASTER_IPA] = &qxm_ipa,
> + [MASTER_MVMSS] = &qxm_mvmss,
> + [MASTER_EMAC_0] = &xm_emac_0,
> + [MASTER_EMAC_1] = &xm_emac_1,
> + [MASTER_QDSS_ETR] = &xm_qdss_etr0,
> + [MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
> + [MASTER_SDCC_1] = &xm_sdc1,
> + [MASTER_SDCC_4] = &xm_sdc4,
> + [MASTER_USB3_0] = &xm_usb3,
> + [SLAVE_ETH0_CFG] = &ps_eth0_cfg,
> + [SLAVE_ETH1_CFG] = &ps_eth1_cfg,
> + [SLAVE_AUDIO] = &qhs_audio,
> + [SLAVE_CLK_CTL] = &qhs_clk_ctl,
> + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
> + [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
> + [SLAVE_IPA_CFG] = &qhs_ipa,
> + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
> + [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
> + [SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg,
> + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
> + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
> + [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
> + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc,
> + [SLAVE_PDM] = &qhs_pdm,
> + [SLAVE_PRNG] = &qhs_prng,
> + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
> + [SLAVE_QPIC] = &qhs_qpic,
> + [SLAVE_QUP_0] = &qhs_qup0,
> + [SLAVE_SDCC_1] = &qhs_sdc1,
> + [SLAVE_SDCC_4] = &qhs_sdc4,
> + [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
> + [SLAVE_TCSR] = &qhs_tcsr,
> + [SLAVE_TLMM] = &qhs_tlmm,
> + [SLAVE_USB3] = &qhs_usb3,
> + [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
> + [SLAVE_A1NOC_CFG] = &qns_a1noc,
> + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
> + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
> + [SLAVE_SNOC_CFG] = &qns_system_noc_cfg,
> + [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg,
> + [SLAVE_IMEM] = &qxs_imem,
> + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc,
> + [SLAVE_SERVICE_SNOC] = &srvc_system_noc,
> + [SLAVE_PCIE_0] = &xs_pcie_0,
> + [SLAVE_PCIE_1] = &xs_pcie_1,
> + [SLAVE_PCIE_2] = &xs_pcie_2,
> + [SLAVE_QDSS_STM] = &xs_qdss_stm,
> + [SLAVE_TCU] = &xs_sys_tcu_cfg,
> +};
> +
> +static struct qcom_icc_desc sdx75_system_noc = {
Come on... we fixed it.
There could be more issues because you used old file as template. Start
from scratch from new file.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings: interconnect: Add compatibles for SDX75
2023-09-05 6:59 ` Krzysztof Kozlowski
@ 2023-09-05 7:14 ` Rohit Agarwal
0 siblings, 0 replies; 7+ messages in thread
From: Rohit Agarwal @ 2023-09-05 7:14 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, djakov,
robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, kernel
On 9/5/2023 12:29 PM, Krzysztof Kozlowski wrote:
> On 05/09/2023 06:59, Rohit Agarwal wrote:
>> Add dt-bindings compatibles and interconnect IDs for
>> Qualcomm SDX75 platform.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>> .../bindings/interconnect/qcom,sdx75-rpmh.yaml | 100 ++++++++++++++++++++
>> include/dt-bindings/interconnect/qcom,sdx75.h | 102 +++++++++++++++++++++
>> 2 files changed, 202 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
>> create mode 100644 include/dt-bindings/interconnect/qcom,sdx75.h
>>
>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
>> new file mode 100644
>> index 0000000..f2dc87c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml
>> @@ -0,0 +1,100 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
>> +
>> +maintainers:
>> + - Georgi Djakov <djakov@kernel.org>
> I don't think Georgi maintains this device. It's maintainer of device,
> not the subsystem.
Ok, Will update the maintainer.
>
>> +
>> +description:
>> + RPMh interconnect providers support system bandwidth requirements through
>> + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
>> + able to communicate with the BCM through the Resource State Coordinator (RSC)
>> + associated with each execution environment. Provider nodes must point to at
>> + least one RPMh device child node pertaining to their RSC and each provider
>> + can map to multiple RPMh resources.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,sdx75-clk-virt
>> + - qcom,sdx75-dc-noc
>> + - qcom,sdx75-gem-noc
>> + - qcom,sdx75-mc-virt
>> + - qcom,sdx75-pcie-anoc
>> + - qcom,sdx75-system-noc
>> +
>> + '#interconnect-cells': true'
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> +allOf:
>> + - $ref: qcom,rpmh-common.yaml#
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sdx75-clk-virt
>> + - qcom,sdx75-mc-virt
>> + then:
>> + properties:
>> + reg: false
>> + else:
>> + required:
>> + - reg
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sdx75-clk-virt
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: RPMH CC QPIC Clock
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sdx75-clk-virt
> This if: clause should be merged with the one earlier.
Ok, understood.
>> + then:
>> + required:
>> + - clocks
>> + else:
>> + properties:
>> + clocks: false
>> +
>> +required:
>> + - compatible
> Please keep the order like in example-schema, so required: goes before
> allOf.
Sure, will update this.
Thanks,
Rohit.
>> +
>> +unevaluatedProperties: false
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] interconnect: qcom: Add SDX75 interconnect provider driver
2023-09-05 7:02 ` Krzysztof Kozlowski
@ 2023-09-05 7:20 ` Rohit Agarwal
0 siblings, 0 replies; 7+ messages in thread
From: Rohit Agarwal @ 2023-09-05 7:20 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, djakov,
robh+dt, krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel, kernel
On 9/5/2023 12:32 PM, Krzysztof Kozlowski wrote:
> On 05/09/2023 06:59, Rohit Agarwal wrote:
>> Add driver for the Qualcomm interconnect buses found in SDX75.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ...
>
>> +
>> +static struct qcom_icc_bcm *system_noc_bcms[] = {
> Please do not copy your code from downstream, but work on upstream. We
> changed this long time ago, so you clearly used some old or obsolete
> file as template.
Sure will check the sm8550 as template and work on it again.
Thank you for your time.
Thanks,
Rohit.
>> + &bcm_ce0,
>> + &bcm_cn0,
>> + &bcm_sn0,
>> + &bcm_sn1,
>> + &bcm_sn2,
>> +};
>> +
>> +static struct qcom_icc_node *system_noc_nodes[] = {
>> + [MASTER_AUDIO] = &qhm_audio,
>> + [MASTER_GIC_AHB] = &qhm_gic,
>> + [MASTER_PCIE_RSCC] = &qhm_pcie_rscc,
>> + [MASTER_QDSS_BAM] = &qhm_qdss_bam,
>> + [MASTER_QPIC] = &qhm_qpic,
>> + [MASTER_QUP_0] = &qhm_qup0,
>> + [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
>> + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
>> + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
>> + [MASTER_SNOC_CFG] = &qnm_system_noc_cfg,
>> + [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg,
>> + [MASTER_CRYPTO] = &qxm_crypto,
>> + [MASTER_IPA] = &qxm_ipa,
>> + [MASTER_MVMSS] = &qxm_mvmss,
>> + [MASTER_EMAC_0] = &xm_emac_0,
>> + [MASTER_EMAC_1] = &xm_emac_1,
>> + [MASTER_QDSS_ETR] = &xm_qdss_etr0,
>> + [MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
>> + [MASTER_SDCC_1] = &xm_sdc1,
>> + [MASTER_SDCC_4] = &xm_sdc4,
>> + [MASTER_USB3_0] = &xm_usb3,
>> + [SLAVE_ETH0_CFG] = &ps_eth0_cfg,
>> + [SLAVE_ETH1_CFG] = &ps_eth1_cfg,
>> + [SLAVE_AUDIO] = &qhs_audio,
>> + [SLAVE_CLK_CTL] = &qhs_clk_ctl,
>> + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
>> + [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
>> + [SLAVE_IPA_CFG] = &qhs_ipa,
>> + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
>> + [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
>> + [SLAVE_ICBDI_MVMSS_CFG] = &qhs_mvmss_cfg,
>> + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
>> + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
>> + [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg,
>> + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc,
>> + [SLAVE_PDM] = &qhs_pdm,
>> + [SLAVE_PRNG] = &qhs_prng,
>> + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
>> + [SLAVE_QPIC] = &qhs_qpic,
>> + [SLAVE_QUP_0] = &qhs_qup0,
>> + [SLAVE_SDCC_1] = &qhs_sdc1,
>> + [SLAVE_SDCC_4] = &qhs_sdc4,
>> + [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
>> + [SLAVE_TCSR] = &qhs_tcsr,
>> + [SLAVE_TLMM] = &qhs_tlmm,
>> + [SLAVE_USB3] = &qhs_usb3,
>> + [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
>> + [SLAVE_A1NOC_CFG] = &qns_a1noc,
>> + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
>> + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
>> + [SLAVE_SNOC_CFG] = &qns_system_noc_cfg,
>> + [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg,
>> + [SLAVE_IMEM] = &qxs_imem,
>> + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc,
>> + [SLAVE_SERVICE_SNOC] = &srvc_system_noc,
>> + [SLAVE_PCIE_0] = &xs_pcie_0,
>> + [SLAVE_PCIE_1] = &xs_pcie_1,
>> + [SLAVE_PCIE_2] = &xs_pcie_2,
>> + [SLAVE_QDSS_STM] = &xs_qdss_stm,
>> + [SLAVE_TCU] = &xs_sys_tcu_cfg,
>> +};
>> +
>> +static struct qcom_icc_desc sdx75_system_noc = {
> Come on... we fixed it.
>
> There could be more issues because you used old file as template. Start
> from scratch from new file.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-09-05 16:26 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-05 4:59 [PATCH 0/2] Add interconnect driver for SDX75 Rohit Agarwal
2023-09-05 4:59 ` [PATCH 1/2] dt-bindings: interconnect: Add compatibles " Rohit Agarwal
2023-09-05 6:59 ` Krzysztof Kozlowski
2023-09-05 7:14 ` Rohit Agarwal
2023-09-05 4:59 ` [PATCH 2/2] interconnect: qcom: Add SDX75 interconnect provider driver Rohit Agarwal
2023-09-05 7:02 ` Krzysztof Kozlowski
2023-09-05 7:20 ` Rohit Agarwal
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox