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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08bcc090sm29612468a91.4.2026.09.07.20.28.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Sep 2026 20:28:28 -0700 (PDT) Message-ID: <43a9f5ec-c8c2-4e3c-bc78-b980ead0ed5a@oss.qualcomm.com> Date: Tue, 8 Sep 2026 11:28:25 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support To: sashiko-reviews@lists.linux.dev Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> <20260906-qcom_ipq5210_cmnpll-v4-7-aec5ed642f4f@oss.qualcomm.com> <20260906142559.17FE91F00A3A@smtp.kernel.org> Content-Language: en-US From: Jie Luo In-Reply-To: <20260906142559.17FE91F00A3A@smtp.kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA4MDAzNCBTYWx0ZWRfXzz4LAkhwqYYr 1cVpazP0INw+OxoWAtyakYKhqtkpEt9LloUG3uuwcnw/9ouZiwYp9SeYD5+p3g8z3nlX7LECSXZ HBJJ8oMeXNnOf8VWWxX7q681LrjyPsZIVrtS5Vn6JTZGp4cg+T728TyVObGzCyxwFxDEM83v0i0 dJMDMVlG32jT9A4CoKItUf9dKSs6v8JJYmWg70dwpE+lVnxWzYJqna4NdcJDN5m2Xqd7D3F7rS6 XH6KZs1Ct8ME8qHCSBCjKf+fbE3gyf7nm44S/L7poo9BjuMJtniZXKshdpJUCm+KqTUqY8fW8kl SacU2hL1jO7O9ijKB2sbgjyxmyencPEM7pK4DfYzaAHB3vRMupIczBrr4CI5vT+gMg54N2hqUtI mPydSch3NhVd9c6kzne2kkVGq/AwMsHm0OGOftN/1aJ+XujP+3alpRv639uwRH5XJYYRepX0Eng dyz3JWwpiKQtkiYC3FA== X-Authority-Analysis: v=2.4 cv=Xbe5Co55 c=1 sm=1 tr=0 ts=6a9f80de cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KbbPYYVOdocP4CsVI9sA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: s9W8mTD1jjMqKENTbhnd52-xantbxRGy X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA4MDAzNCBTYWx0ZWRfX2aQ3lVxwjjGe 5XDXyzDfy+lT2BigNmTGw96t5UQqAcfgRBtdLHuL2QWHGTcGFzGiwQ+0a+DauqvY1rSkd5mgSDL o56ypKVZK1aH6Sw03Rvz24ER39mpbLo= X-Proofpoint-GUID: s9W8mTD1jjMqKENTbhnd52-xantbxRGy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_07,2026-09-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501 spamscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609080034 On 9/6/2026 10:25 PM, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [High] clk_pon_clk_determine_rate() incorrectly fails valid rate requests due to rounding at bound edges. > -- > > commit 9a9a4823a8ebca7e3c30590799eb2ac41ada876e > Author: Luo Jie > > clk: qcom: ipq-cmn-pll: Add PON reference clock support > > This commit adds support for the PON reference clock to the IPQ CMN PLL driver. > It configures the clock to operate in either UNIPHY mode with a fixed 31.25 MHz > rate, or PON mode using an 8-bit divider derived from the parent rate. > >> diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c >> index 44d035870a89b..f12352a707f7a 100644 >> --- a/drivers/clk/qcom/ipq-cmn-pll.c >> +++ b/drivers/clk/qcom/ipq-cmn-pll.c > [ ... ] >> +static int clk_pon_clk_determine_rate(struct clk_hw *hw, >> + struct clk_rate_request *req) >> +{ >> + unsigned long div, pon_rate, uniphy_rate = 31250000UL; >> + bool uniphy_rate_valid, pon_rate_valid; >> + >> + if (!req->rate || !req->best_parent_rate) >> + return -EINVAL; >> + >> + div = DIV64_U64_ROUND_CLOSEST((u64)req->best_parent_rate, req->rate); >> + >> + /* Clamp to valid range (1-255) */ >> + div = clamp_t(unsigned long, div, 1, 255); >> + >> + pon_rate = DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, div); >> + >> + uniphy_rate_valid = uniphy_rate >= req->min_rate && >> + uniphy_rate <= req->max_rate; >> + pon_rate_valid = pon_rate >= req->min_rate && >> + pon_rate <= req->max_rate; >> + >> + if (!uniphy_rate_valid && !pon_rate_valid) >> + return -EINVAL; > > [Severity: High] > Will this logic incorrectly reject valid rate requests when the closest > divider falls slightly outside the boundaries due to rounding? > > If a client restricts the bounds (e.g., via clk_set_min_rate), the requested > rate is clamped to the bounds. If calculating the closest divider for that > rate yields a frequency that barely misses the min_rate or max_rate bound, > pon_rate_valid becomes false and this returns -EINVAL. > > Should this code check adjacent dividers (such as div - 1 or div + 1) to see > if they yield a rate strictly within the requested bounds before giving up? > It doesn't hold up for this driver, a PON reference clock feeds the UNIPHY/PON that needs one exact standard frequency (e.g. the 31.25 MHz UNIPHY rate, or whatever exact PON-mode rate the line rate dictates), not "anything within a window." A real consumer would call clk_set_rate(clk, exact_rate) and expect either that exact rate back or -EINVAL, never clk_set_rate_range(). >> + >> + /* Pick whichever mode gets closer to the requested rate */ >> + if (uniphy_rate_valid && pon_rate_valid) { > [ ... ] >