From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54B301367; Wed, 28 May 2025 07:25:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748417142; cv=none; b=bxj4bsOjUH9LyTqwVdPcQURVKvrt8b/X7x9fkLL0aN+mUeTSPeTnkc7Td/6nOUsVBPmrDbxmEJQvujW+2SjuajpeYXv8gzDEjlcXBVp0rOwHO9/ehSCj26hdgPxbBd8hU4Y5YYmTSIVggTTgssYjiCMtGriPFlzTzjcuwtTAj5Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748417142; c=relaxed/simple; bh=4oYNcof0NvsL8+KTpTf/6kMf6BWKIsxqMPsWFf9O4mA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NuoylqEhCd6eD3lB7iAUS4C6l/PhdIrXe4qjXAag7Dw76NE/7qS6hQgZ7A514sq9YIFANRLWwoRVvkLdUOUSqu4dhUGr/ZEjj4QkjvnDg0iWruwlUn0jidpMdJOEf42KR1tJrAW4SlAS5yURkKTJqO4nLhglGjS8n1zmHxwql6c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A3xfTqv/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A3xfTqv/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5639FC4CEE7; Wed, 28 May 2025 07:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748417141; bh=4oYNcof0NvsL8+KTpTf/6kMf6BWKIsxqMPsWFf9O4mA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=A3xfTqv/aRqe3q/tUZrThHNI+nMFY318R4H/TLQCQ9vWKOB/H/bnAVOoN3AsHO5tG 9PbV2nLbbxG5BKqFdgkleiVdySiRtW09ifX5uJQhaWh8eM7A4qM1yN3irbHJ2mTYES lCXkU0EI+H5mmhW+yGZsiX13kAVn/o+ncr+hcNUi0bLSJuwwgNr37JpWrPadwVtc8t TXqhrAXQoGH1av837RuoHqTI15rQHFTP4hKcat63hjdXpoylWWdAVWR4uRUsIa7ymx yJGv3L5MVaGO0qEGAN0e055fXDqTeq+mWcoN/Dx9T1EhzG5cem9dvuiUsV9qlncR6+ 9sUiEPKftXiYA== Message-ID: <441dd5c3-fd51-4471-86ad-337c646b1571@kernel.org> Date: Wed, 28 May 2025 09:25:35 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC To: Shradha Todi Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com References: <20250518193152.63476-1-shradha.t@samsung.com> <20250518193152.63476-10-shradha.t@samsung.com> <20250521-competent-honeybee-of-will-3f3ae1@kuoka> <0e2801dbcef4$78fe5ec0$6afb1c40$@samsung.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 27/05/2025 12:45, Shradha Todi wrote: > > >> -----Original Message----- >> From: Krzysztof Kozlowski >> Sent: 21 May 2025 15:18 >> To: Shradha Todi >> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.or; >> linux-kernel@vger.kernel.org; linux-phy@lists.infradead.org; manivannan.sadhasivam@linaro.org; lpieralisi@kernel.org; >> kw@linux.com; robh@kernel.org; bhelgaas@google.com; jingoohan1@gmail.com; krzk+dt@kernel.org; conor+dt@kernel.org; >> alim.akhtar@samsung.com; vkoul@kernel.org; kishon@kernel.org; arnd@arndb.de; m.szyprowski@samsung.com; >> jh80.chung@samsung.com >> Subject: Re: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC >> >> On Mon, May 19, 2025 at 01:01:51AM GMT, Shradha Todi wrote: >>> static int exynos_pcie_probe(struct platform_device *pdev) { >>> struct device *dev = &pdev->dev; >>> @@ -355,6 +578,26 @@ static int exynos_pcie_probe(struct platform_device *pdev) >>> if (IS_ERR(ep->phy)) >>> return PTR_ERR(ep->phy); >>> >>> + if (ep->pdata->soc_variant == FSD) { >>> + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); >>> + if (ret) >>> + return ret; >>> + >>> + ep->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, >>> + "samsung,syscon-pcie"); >>> + if (IS_ERR(ep->sysreg)) { >>> + dev_err(dev, "sysreg regmap lookup failed.\n"); >>> + return PTR_ERR(ep->sysreg); >>> + } >>> + >>> + ret = of_property_read_u32_index(dev->of_node, "samsung,syscon-pcie", 1, >>> + &ep->sysreg_offset); >>> + if (ret) { >>> + dev_err(dev, "couldn't get the register offset for syscon!\n"); >> >> So all MMIO will go via syscon? I am pretty close to NAKing all this, but let's be sure that I got it right - please post your complete DTS >> for upstream. That's a requirement from me for any samsung drivers - I don't want to support fake, broken downstream solutions >> (based on multiple past submissions). >> > > By all MMIO do you mean DBI read/write? The FSD hardware architecture is such that the DBI/ATU/DMA address is at the same offset. > The syscon register holds the upper bits of the actual address differentiating between these 3 spaces. This kind of implementation was done > to reduce address space for PCI DWC controller. So yes, each DBI/ATU register read/write will have syscon write before it to switch address space. Wrap your replies correctly to fit mailing list. No, I meant your binding does not define any MMIO at all. I see you use for example elbi_base which is mapped from "elbi" reg entry, but you do not have it in your binding. Maybe just binding is heavily incomplete and that confused me. Best regards, Krzysztof