From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Ap7yNQ2m" Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5A2DFF for ; Sat, 25 Nov 2023 07:17:15 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4083f61312eso22485465e9.3 for ; Sat, 25 Nov 2023 07:17:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700925434; x=1701530234; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=L//cXM65lEufA8qopdoTlT0G7CECObDXCb5waukCjRo=; b=Ap7yNQ2moSOX+8m5uas3PtuT63QBqWm6/dD8H9jpRPFgLvz2j41AxuYzYlG0yUT5lV 0qgjyt0H35yUQaGz1Z5kIxSHfSiy6RDgF+aFd0sxZOHMuPgthx2lHoj6MfMDmaRSkV6E qyJBvAxQKuF/zDHeBf4I96rnj13bzHSmsnVW/ZKVZ8jLQG32M/i55hnyFLfBYJP7bAbq g4ASPA3UO5MwqKWgf/mkL+iYjKOlBLv/nslgMnuEUljzRvbsdtLhbDwXb3g/1cDQdfeF rD0blYYsMuAtVA3W/iiIwao5+2A1wbuwFk/f4xk3FwMeH4Kf32FjPJIUwu59TJmJwQGu truw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700925434; x=1701530234; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=L//cXM65lEufA8qopdoTlT0G7CECObDXCb5waukCjRo=; b=SfK5qh5RyATxvUzWmkYpmEBDJRnDiYFFnY3ZIToUOWKxLG8akQcK45LOltOsDctXfn JzLJ+39PdwmCSEEvD2qN375x5nXZTW0hMs1wq72fU9TgdHvDi/2w6+523x+r4Da9q3Vq yh8KI9Pb14au5eFTjhVrAIHKwYBnSBC1OoBa8sRCgOe3dId3Qnnr6DXh+K1Khd1rp2m/ Dn1Y6GLpaO50js6TnN/n5FnMwaz59x/nxdwheMxaRSOfOsQwq35mFKAG+MtlKZcUztyQ 8ZUVYIcOAk56uDvLrzTY+Q2oAKeWgoQm8IqUPNIgER9kbszt1Sgp2D5Ue5PEqYQUJsbZ QgEw== X-Gm-Message-State: AOJu0YyxnStcV9TM5N8IAXugdDMzVlVbOT4t8O880PWhdPwbQyswos2b M0ZYkKP13ebqgw0joebDkD7Bag== X-Google-Smtp-Source: AGHT+IGwnqLhrtr72VZNjFVnj7zkFww47Kvwg5iba4kzHIGXaWjdDtnp+7LshXKgBUTTBwgApNkbpA== X-Received: by 2002:a05:600c:3550:b0:40b:415e:c044 with SMTP id i16-20020a05600c355000b0040b415ec044mr1056018wmq.37.1700925434011; Sat, 25 Nov 2023 07:17:14 -0800 (PST) Received: from [192.168.100.102] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id a10-20020a056000050a00b0032ddf2804ccsm6798220wrf.83.2023.11.25.07.17.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Nov 2023 07:17:13 -0800 (PST) Message-ID: <44a2b30a-7f8c-44a9-8a74-b09fee2b61b7@linaro.org> Date: Sat, 25 Nov 2023 15:17:12 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space Content-Language: en-US To: Konrad Dybcio , Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> <20230328-topic-msgram_mpm-v6-2-682e4855b7e2@linaro.org> From: Bryan O'Donoghue In-Reply-To: <20230328-topic-msgram_mpm-v6-2-682e4855b7e2@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 25/11/2023 14:27, Konrad Dybcio wrote: > The MPM hardware is accessible to us from the ARM CPUs through a shared > memory region (RPM MSG RAM) that's also concurrently accessed by other > kinds of cores on the system (like modem, ADSP etc.). Modeling this > relation in a (somewhat) sane manner in the device tree basically > requires us to either present the MPM as a child of said memory region > (which makes little sense, as a mapped memory carveout is not a bus), > define nodes which bleed their register spaces into one another, or > passing their slice of the MSG RAM through some kind of a property. > > Go with the third option and add a way to map a region passed through > the "qcom,rpm-msg-ram" property as our register space. > > The current way of using 'reg' is preserved for ABI reasons. > > Acked-by: Shawn Guo > Signed-off-by: Konrad Dybcio > --- > drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- > 1 file changed, 18 insertions(+), 3 deletions(-) > > diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c > index 7124565234a5..7115e3056aa5 100644 > --- a/drivers/irqchip/irq-qcom-mpm.c > +++ b/drivers/irqchip/irq-qcom-mpm.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) > struct device *dev = &pdev->dev; > struct irq_domain *parent_domain; > struct generic_pm_domain *genpd; > + struct device_node *msgram_np; > struct qcom_mpm_priv *priv; > unsigned int pin_cnt; > + struct resource res; > int i, irq; > int ret; > > @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) > > raw_spin_lock_init(&priv->lock); > > - priv->base = devm_platform_ioremap_resource(pdev, 0); > - if (IS_ERR(priv->base)) > - return PTR_ERR(priv->base); > + /* If we have a handle to an RPM message ram partition, use it. */ > + msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); > + if (msgram_np) { > + ret = of_address_to_resource(msgram_np, 0, &res); You are capturing the return value but doing nothing with it. One of if (ret) { of_node_put(msgram_np); return ret; } or just drop the ret = if you are sure of_address_to_resource() can never return an error for your use-case. Once fixed. Reviewed-by: Bryan O'Donoghue