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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id i38-20020a0565123e2600b0050bf789f501sm29324lfv.11.2023.12.07.11.47.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 Dec 2023 11:47:48 -0800 (PST) Message-ID: <44c36d3f-dacd-4ca9-b92a-5febdc5d1340@linaro.org> Date: Thu, 7 Dec 2023 20:47:46 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm8650: Add DisplayPort device nodes Content-Language: en-US To: Neil Armstrong , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20231207-topic-sm8650-upstream-dp-v1-0-b762c06965bb@linaro.org> <20231207-topic-sm8650-upstream-dp-v1-3-b762c06965bb@linaro.org> From: Konrad Dybcio In-Reply-To: <20231207-topic-sm8650-upstream-dp-v1-3-b762c06965bb@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/7/23 17:37, Neil Armstrong wrote: > Declare the displayport controller present on the Qualcomm SM8650 SoC > and connected to the USB3/DP Combo PHY. > > Signed-off-by: Neil Armstrong > --- [...] > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; What about PIXEL1 clocks? [...] > + opp-162000000 { > + opp-hz = /bits/ 64 <162000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > }; > > dispcc: clock-controller@af00000 { > @@ -2996,8 +3086,8 @@ dispcc: clock-controller@af00000 { > <&mdss_dsi0_phy 1>, > <&mdss_dsi1_phy 0>, > <&mdss_dsi1_phy 1>, > - <0>, /* dp0 */ > - <0>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, > <0>, /* dp1 */ > <0>, > <0>, /* dp2 */ I noticed that this is not in line with your mdss patch [1] where there are only two DP INTFs available.. Unless all of these controllers can work using some sharing/only some at one time... Konrad [1] https://lore.kernel.org/all/20231030-topic-sm8650-upstream-mdss-v2-5-43f1887c82b8@linaro.org/