Re: [PATCH v3 07/13] arm64: dts: mediatek: mt7988: add switch node

AngeloGioacchino Del Regno
2025-06-11T09:33:54Z

Il 08/06/25 23:14, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> Add mt7988 builtin mt753x switch nodes.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> v2:
> - drop labels and led-function too (have to be in board)
> ---
> arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 153 ++++++++++++++++++++++
> 1 file changed, 153 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index ee1e01d720fe..0b35a32b9c89 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -742,6 +742,159 @@ ethsys: clock-controller@15000000 {
> #reset-cells = <1>;
> };
>
> + switch: switch@15020000 {
> + compatible = "mediatek,mt7988-switch";
> + reg = <0 0x15020000 0 0x8000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;

You don't need interrupt-parent, it's already GIC here... :-)

> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_port0: port@0 {
> + reg = <0>;

Keep it ordered alphabetically - phy-handle (h) before phy-mode (m)

> + phy-mode = "internal";
> + phy-handle = <&gsw_phy0>;
> + };
> +
> + gsw_port1: port@1 {
> + reg = <1>;
> + phy-mode = "internal";
> + phy-handle = <&gsw_phy1>;
> + };
> +
> + gsw_port2: port@2 {
> + reg = <2>;
> + phy-mode = "internal";
> + phy-handle = <&gsw_phy2>;
> + };
> +
> + gsw_port3: port@3 {
> + reg = <3>;
> + phy-mode = "internal";
> + phy-handle = <&gsw_phy3>;
> + };
> +
> + port@6 {
> + reg = <6>;
> + ethernet = <&gmac0>;
> + phy-mode = "internal";
> +
> + fixed-link {
> + speed = <10000>;
> + full-duplex;
> + pause;
> + };
> + };
> + };
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mediatek,pio = <&pio>;
> +
> + gsw_phy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + interrupts = <0>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p0>;
> + nvmem-cell-names = "phy-cal-data";

phy-mode (p) after nvmem-cell-names (n) please (here and everywhere else)

> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy0_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy0_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + gsw_phy1: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + interrupts = <1>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p1>;
> + nvmem-cell-names = "phy-cal-data";
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy1_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy1_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + gsw_phy2: ethernet-phy@2 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <2>;
> + interrupts = <2>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p2>;
> + nvmem-cell-names = "phy-cal-data";
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy2_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy2_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + gsw_phy3: ethernet-phy@3 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <3>;
> + interrupts = <3>;
> + phy-mode = "internal";
> + nvmem-cells = <&phy_calibration_p3>;
> + nvmem-cell-names = "phy-cal-data";
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_phy3_led0: led@0 {
> + reg = <0>;
> + status = "disabled";
> + };
> +
> + gsw_phy3_led1: led@1 {
> + reg = <1>;
> + status = "disabled";
> + };
> + };
> + };
> + };
> + };
> +
> ethwarp: clock-controller@15031000 {
> compatible = "mediatek,mt7988-ethwarp";
> reg = <0 0x15031000 0 0x1000>;