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[82.149.1.233]) by smtp.gmail.com with ESMTPSA id 22-20020a05600c22d600b003fe2de3f94fsm3063043wmg.12.2023.08.04.12.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 12:05:38 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: Icenowy Zheng , Piotr Oniszczuk , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/3] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board support Date: Fri, 04 Aug 2023 21:05:36 +0200 Message-ID: <4500165.LvFx2qVVIh@jernej-laptop> In-Reply-To: <20230804170856.1237202-4-andre.przywara@arm.com> References: <20230804170856.1237202-1-andre.przywara@arm.com> <20230804170856.1237202-4-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Dne petek, 04. avgust 2023 ob 19:08:56 CEST je Andre Przywara napisal(a): > The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC, > which seems to be just an H616 with more L2 cache. The board itself is a > slightly updated version of the Orange Pi Zero 2. It features: > - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU > - 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2) > - AXP313a PMIC (more capable AXP305 on the Zero2) > - Raspberry-Pi-1 compatible GPIO header > - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports > - 1 USB 2.0 host port > - 1 USB 2.0 type C port (power supply + OTG) > - MicroSD slot > - on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2) > - 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2) > - micro-HDMI port > - (yet) unsupported Allwinner WiFi/BT chip > > Add the devicetree file describing the currently supported features, > namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at > the moment, though the basic functionality works. > > Signed-off-by: Andre Przywara > --- > arch/arm64/boot/dts/allwinner/Makefile | 1 + > .../allwinner/sun50i-h618-orangepi-zero3.dts | 94 +++++++++++++++++++ > 2 files changed, 95 insertions(+) > create mode 100644 > arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts > > diff --git a/arch/arm64/boot/dts/allwinner/Makefile > b/arch/arm64/boot/dts/allwinner/Makefile index 6a96494a2e0a3..3b0ad54062381 > 100644 > --- a/arch/arm64/boot/dts/allwinner/Makefile > +++ b/arch/arm64/boot/dts/allwinner/Makefile > @@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts > b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts new file > mode 100644 > index 0000000000000..96a6851728111 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts > @@ -0,0 +1,94 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2023 Arm Ltd. > + */ > + > +/dts-v1/; > + > +#include "sun50i-h616-orangepi-zero.dtsi" > + > +/ { > + model = "OrangePi Zero3"; > + compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; > +}; > + > +&emac0 { > + phy-supply = <®_dldo1>; > +}; > + > +&ext_rgmii_phy { > + motorcomm,clk-out-frequency-hz = <125000000>; > +}; > + > +&mmc0 { > + /* > + * The schematic shows the card detect pin wired up to PF6, via an > + * inverter, but it just doesn't work. > + */ > + broken-cd; > + vmmc-supply = <®_dldo1>; > +}; > + > +&r_i2c { > + status = "okay"; > + > + axp313: pmic@36 { > + compatible = "x-powers,axp313a"; > + reg = <0x36>; > + #interrupt-cells = <1>; > + interrupt-controller; > + interrupt-parent = <&pio>; > + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ > + > + vin1-supply = <®_vcc5v>; > + vin2-supply = <®_vcc5v>; > + vin3-supply = <®_vcc5v>; > + > + regulators { > + /* Supplies VCC-PLL, so needs to be always on. */ > + reg_aldo1: aldo1 { > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-name = "vcc1v8"; > + }; > + > + /* Supplies VCC-IO, so needs to be always on. */ > + reg_dldo1: dldo1 { > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc3v3"; > + }; > + > + reg_dcdc1: dcdc1 { > + regulator-always-on; > + regulator-min-microvolt = <810000>; > + regulator-max-microvolt = <990000>; > + regulator-name = "vdd-gpu-sys"; > + }; Is it safe to change sys voltage when system is running? Best regards, Jernej > + > + reg_dcdc2: dcdc2 { > + regulator-always-on; > + regulator-min-microvolt = <810000>; > + regulator-max-microvolt = <1100000>; > + regulator-name = "vdd-cpu"; > + }; > + > + reg_dcdc3: dcdc3 { > + regulator-always-on; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + regulator-name = "vdd-dram"; > + }; > + }; > + }; > +}; > + > +&pio { > + vcc-pc-supply = <®_dldo1>; > + vcc-pf-supply = <®_dldo1>; > + vcc-pg-supply = <®_aldo1>; > + vcc-ph-supply = <®_dldo1>; > + vcc-pi-supply = <®_dldo1>; > +};