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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id em3-20020a056402364300b00458824aee80sm2334858edb.38.2022.11.06.01.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 01:25:56 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Samuel Holland , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Andre Przywara Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng , Hans de Goede , Dmitry Torokhov , linux-input@vger.kernel.org Subject: Re: [PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node Date: Sun, 06 Nov 2022 09:25:55 +0100 Message-ID: <45074583.fMDQidcC6G@jernej-laptop> In-Reply-To: <20221101141658.3631342-10-andre.przywara@arm.com> References: <20221101141658.3631342-1-andre.przywara@arm.com> <20221101141658.3631342-10-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Dne torek, 01. november 2022 ob 15:16:58 CET je Andre Przywara napisal(a): > The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) > compatible to the version in other SoCs. > The manual doesn't mention the ratio of the input voltage that is used, > but comparing actual measurements with the values in the register > suggests that it is 3/4 of Vref. > > Add the DT node describing the base address and interrupt. As in the > older SoCs, there is no explicit reset or clock gate, also there is a > dedicated, non-multiplexed pin, so need for more properties. > > Signed-off-by: Andre Przywara > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d29b48f23b89a..03592c8e63fed > 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -262,6 +262,14 @@ ir: ir@1c22c00 { > status = "disabled"; > }; > > + lradc: lradc@1c23400 { > + compatible = "allwinner,suniv-f1c100s- lradc", > + "allwinner,sun8i-a83t-r- lradc"; > + reg = <0x01c23400 0x100>; User manual says 0x400 is reserved for this peripheral. With that fixed: Reviewed-by: Jernej Skrabec Best regards, Jernej > + interrupts = <22>; > + status = "disabled"; > + }; > + > uart0: serial@1c25000 { > compatible = "snps,dw-apb-uart"; > reg = <0x01c25000 0x400>;