Re: [PATCH] clk: rs9: Fix DIF OEn bit placement on 9FGV0241

Stephen Boyd
2023-12-17T22:10:28Z

Quoting Marek Vasut (2023-11-05 12:06:15)
> On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other
> chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment
> the index in BIT() macro instead of the result of BIT() macro to shift
> the bit correctly on 9FGV0241.
>
> Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation")
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---

Applied to clk-next