[PATCH 0/2] rockchip pcie3-phy separate refclk support

Niklas Cassel
2024-04-11T13:01:57Z

This series is based on: linux-phy phy/fixes
(Since there are other rockchip,pcie3-phy changes there that have not
yet reached mainline and which would otherwise have caused conflicts.)

Hello all,

The rockchip,pcie3-phy PHY in rk3588 is by default configured to run in
"common reference clock" mode. (Which is a sensible default, as the most
commonly used clock configuration is "common reference clock".)

However, PCIe also defines two other configurations where the Root Complex
and Endpoint uses separate reference clocks: SRNS and SRIS.

Having the Root Complex PHY configured in "common reference clock mode"
while having an Endpoint connected which is supplying its own reference
clock (i.e. SRNS or SRIS configuration), will either result in the link
training failing, or a highly unstable link that continuously jumps
between link states L0 and recovery.

Add a rockchip specific device tree property that can be added to the
rk3588 Root Complex device tree PHY node, if the connected Endpoint device
is using a separate refererence clock. This way we will get a stable link
when using an Endpoint configured in SRNS or SRIS mode.

Kind regards,
Niklas

Niklas Cassel (2):
dt-bindings: phy: rockchip,pcie3-phy: add
rockchip,rx-common-refclk-mode
phy: rockchip-snps-pcie3: add support for
rockchip,rx-common-refclk-mode

.../bindings/phy/rockchip,pcie3-phy.yaml | 10 +++++
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++
2 files changed, 47 insertions(+)

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2.44.0