* [PATCH v3 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq
2023-04-21 3:14 [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo
@ 2023-04-21 3:14 ` Mason Huo
2023-04-21 3:14 ` [PATCH v3 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Mason Huo @ 2023-04-21 3:14 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
The VisionFive 2 board has an embedded pmic axp15060,
which supports the cpu DVFS through the dcdc2 regulator.
This patch enables axp15060 pmic and configs the dcdc2.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..cca1c8040801 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -114,6 +114,20 @@ &i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
status = "okay";
+
+ axp15060: pmic@36 {
+ compatible = "x-powers,axp15060";
+ reg = <0x36>;
+
+ regulators {
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ regulator-name = "vdd-cpu";
+ };
+ };
+ };
};
&i2c6 {
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v3 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
2023-04-21 3:14 [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-21 3:14 ` [PATCH v3 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
@ 2023-04-21 3:14 ` Mason Huo
2023-04-21 7:37 ` Viresh Kumar
2023-04-21 3:14 ` [PATCH v3 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
2023-05-05 1:38 ` [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo
3 siblings, 1 reply; 9+ messages in thread
From: Mason Huo @ 2023-04-21 3:14 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the compatible strings for supporting the generic
cpufreq driver on the StarFive JH7110 SoC.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index e85703651098..79537d0ed7cf 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -86,6 +86,8 @@ static const struct of_device_id allowlist[] __initconst = {
{ .compatible = "st-ericsson,u9500", },
{ .compatible = "st-ericsson,u9540", },
+ { .compatible = "starfive,jh7110", },
+
{ .compatible = "ti,omap2", },
{ .compatible = "ti,omap4", },
{ .compatible = "ti,omap5", },
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
2023-04-21 3:14 ` [PATCH v3 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
@ 2023-04-21 7:37 ` Viresh Kumar
0 siblings, 0 replies; 9+ messages in thread
From: Viresh Kumar @ 2023-04-21 7:37 UTC (permalink / raw)
To: Mason Huo
Cc: Rafael J. Wysocki, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Shengyu Qu, linux-pm, devicetree, linux-kernel,
linux-riscv
On 21-04-23, 11:14, Mason Huo wrote:
> Add the compatible strings for supporting the generic
> cpufreq driver on the StarFive JH7110 SoC.
>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
> drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index e85703651098..79537d0ed7cf 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -86,6 +86,8 @@ static const struct of_device_id allowlist[] __initconst = {
> { .compatible = "st-ericsson,u9500", },
> { .compatible = "st-ericsson,u9540", },
>
> + { .compatible = "starfive,jh7110", },
> +
> { .compatible = "ti,omap2", },
> { .compatible = "ti,omap4", },
> { .compatible = "ti,omap5", },
Applied. Thanks.
--
viresh
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
2023-04-21 3:14 [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-21 3:14 ` [PATCH v3 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
2023-04-21 3:14 ` [PATCH v3 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
@ 2023-04-21 3:14 ` Mason Huo
2023-05-05 1:38 ` [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo
3 siblings, 0 replies; 9+ messages in thread
From: Mason Huo @ 2023-04-21 3:14 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv,
Mason Huo
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 16 +++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index cca1c8040801..43a9dbb839d2 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -227,3 +227,19 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&U74_1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+ cpu-supply = <&vdd_cpu>;
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7eef88d2cedb 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,9 @@ U74_1: cpu@1 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -79,6 +82,9 @@ U74_2: cpu@2 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -105,6 +111,9 @@ U74_3: cpu@3 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -131,6 +140,9 @@ U74_4: cpu@4 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -164,6 +176,27 @@ core4 {
};
};
+ cpu_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1040000>;
+ };
+ };
+
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
--
2.39.2
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v3 0/3] Add JH7110 cpufreq support
2023-04-21 3:14 [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo
` (2 preceding siblings ...)
2023-04-21 3:14 ` [PATCH v3 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
@ 2023-05-05 1:38 ` Mason Huo
2023-05-05 6:29 ` Conor Dooley
3 siblings, 1 reply; 9+ messages in thread
From: Mason Huo @ 2023-05-05 1:38 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou
Cc: Shengyu Qu, linux-pm, devicetree, linux-kernel, linux-riscv
Hi Conor & Shengyu,
Thanks for your review, and is there any comments about these v3 patches?
Thanks
Mason
On 2023/4/21 11:14, Mason Huo wrote:
> The StarFive JH7110 SoC has four RISC-V cores,
> and it supports up to 4 cpu frequency loads.
>
> This patchset adds the compatible strings into the allowlist
> for supporting the generic cpufreq driver on JH7110 SoC.
> Also, it enables the axp15060 pmic for the cpu power source.
>
> The series has been tested on the VisionFive 2 boards which
> are equipped with JH7110 SoC and axp15060 pmic.
>
>
> This patchset is based on v6.3-rc4 with these patches applied:
> [1] ("Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC")
> https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/
> [2] ("Add X-Powers AXP15060 PMIC support")
> https://lore.kernel.org/all/TY3P286MB2611A814E580C96DC6F187B798969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
>
> Changes since v2:
> - Fix the new blank line at EOF issue in dtsi.
>
> Changes since v1:
> - Fix dts node naming issues.
> - Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
> - Follow the alphabetical order to place the cpufreq dt allowlist.
>
> ---
> v1: https://lore.kernel.org/all/20230411083257.16155-1-mason.huo@starfivetech.com/
> v2: https://lore.kernel.org/lkml/20230417063942.3141-1-mason.huo@starfivetech.com/
>
> Mason Huo (3):
> riscv: dts: starfive: Enable axp15060 pmic for cpufreq
> cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
> riscv: dts: starfive: Add cpu scaling for JH7110 SoC
>
> .../jh7110-starfive-visionfive-2.dtsi | 30 +++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
> drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
> 3 files changed, 65 insertions(+)
>
> base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v3 0/3] Add JH7110 cpufreq support
2023-05-05 1:38 ` [PATCH v3 0/3] Add JH7110 cpufreq support Mason Huo
@ 2023-05-05 6:29 ` Conor Dooley
2023-06-05 9:36 ` Mason Huo
0 siblings, 1 reply; 9+ messages in thread
From: Conor Dooley @ 2023-05-05 6:29 UTC (permalink / raw)
To: Mason Huo
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm, devicetree,
linux-kernel, linux-riscv
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On Fri, May 05, 2023 at 09:38:38AM +0800, Mason Huo wrote:
> Hi Conor & Shengyu,
>
> Thanks for your review, and is there any comments about these v3 patches?
Firstly there appears to have been some mess-up with the driver/bindings
for 1/3, so I am waiting to see if the binding gets reverted before
doing anything and secondly it's the merge window so I can't do anything
about 3/3 until next week.
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/3] Add JH7110 cpufreq support
2023-05-05 6:29 ` Conor Dooley
@ 2023-06-05 9:36 ` Mason Huo
2023-06-05 9:54 ` Conor Dooley
0 siblings, 1 reply; 9+ messages in thread
From: Mason Huo @ 2023-06-05 9:36 UTC (permalink / raw)
To: Conor Dooley
Cc: Rafael J. Wysocki, Viresh Kumar, Emil Renner Berthing,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Shengyu Qu, linux-pm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Hi Conor,
> On Fri, May 05, 2023 at 09:38:38AM +0800, Mason Huo wrote:
>> Hi Conor & Shengyu,
>>
>> Thanks for your review, and is there any comments about these v3 patches?
> Firstly there appears to have been some mess-up with the driver/bindings for 1/3, so I am waiting to see if the binding gets reverted before doing anything and secondly it's the merge window so I can't do anything about 3/3 until next week.
>
> Cheers,
> Conor.
Could you help to check if this patch can be moved on?
Thanks
Mason
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/3] Add JH7110 cpufreq support
2023-06-05 9:36 ` Mason Huo
@ 2023-06-05 9:54 ` Conor Dooley
0 siblings, 0 replies; 9+ messages in thread
From: Conor Dooley @ 2023-06-05 9:54 UTC (permalink / raw)
To: Mason Huo
Cc: Conor Dooley, Rafael J. Wysocki, Viresh Kumar,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Shengyu Qu,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
[-- Attachment #1: Type: text/plain, Size: 2087 bytes --]
On Mon, Jun 05, 2023 at 09:36:51AM +0000, Mason Huo wrote:
> > On Fri, May 05, 2023 at 09:38:38AM +0800, Mason Huo wrote:
> >> Thanks for your review, and is there any comments about these v3 patches?
>
> > Firstly there appears to have been some mess-up with the driver/bindings
> > for 1/3, so I am waiting to see if the binding gets reverted before
> > doing anything and secondly it's the merge window so I can't do anything
> > about 3/3 until next week.
> Could you help to check if this patch can be moved on?
The dependencies are in, I guess when I went checking through things on
patchwork after the merge window I spotted some issue & didn't reply to
the patch. So sorry about that.
The issue that I must've spotted is that patch 1/3 doesn't pass
dtbs_check:
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: pmic@36: 'interrupts' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: pmic@36: '#interrupt-cells' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: pmic@36: 'interrupt-controller' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: pmic@36: 'interrupts' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: pmic@36: '#interrupt-cells' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: pmic@36: 'interrupt-controller' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
Could you please fix that up & resend the 2 unapplied patches?
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 9+ messages in thread