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Thu, 23 Nov 2023 07:13:26 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AN7DPe2021541 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 07:13:25 GMT Received: from [10.216.58.146] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 23:13:17 -0800 Message-ID: <459005b7-df82-48c1-a85f-d4125ddde124@quicinc.com> Date: Thu, 23 Nov 2023 12:43:12 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC To: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , References: <20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com> <20231121-ipq5332-nsscc-v2-8-a7ff61beab72@quicinc.com> <8cece5d7-0fcb-4366-be72-6494842b7c41@linaro.org> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <8cece5d7-0fcb-4366-be72-6494842b7c41@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: V7vh9dVEOWNCbszbHchbgdNhNVn2IHq- X-Proofpoint-ORIG-GUID: V7vh9dVEOWNCbszbHchbgdNhNVn2IHq- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_04,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 mlxscore=0 adultscore=0 bulkscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311230049 On 11/23/2023 1:52 AM, Konrad Dybcio wrote: > > > On 11/21/23 15:30, Kathiravan Thirumoorthy wrote: >> Describe the NSS clock controller node and it's relevant external >> clocks. >> >> Signed-off-by: Kathiravan Thirumoorthy >> --- >> Changes in V2: >>     - Update the node names with proper suffix >> --- >>   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ >>   1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> index 42e2e48b2bc3..5cbe72f03869 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> @@ -15,6 +15,18 @@ / { >>       #size-cells = <2>; >>       clocks { >> +        cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk { >> +            compatible = "fixed-clock"; >> +            clock-frequency = <200000000>; >> +            #clock-cells = <0>; >> +        }; >> + >> +        cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk { >> +            compatible = "fixed-clock"; >> +            clock-frequency = <300000000>; >> +            #clock-cells = <0>; >> +        }; >> + >>           sleep_clk: sleep-clk { >>               compatible = "fixed-clock"; >>               #clock-cells = <0>; >> @@ -473,6 +485,22 @@ frame@b128000 { >>                   status = "disabled"; >>               }; >>           }; >> + >> +        nsscc: clock-controller@39b00000{ >> +            compatible = "qcom,ipq5332-nsscc"; >> +            reg = <0x39b00000 0x80000>; >> +            clocks = <&cmn_pll_nss_200m_clk>, >> +                 <&cmn_pll_nss_300m_clk>, >> +                 <&gcc GPLL0_OUT_AUX>, >> +                 <0>, >> +                 <0>, >> +                 <0>, >> +                 <0>, >> +                 <&xo_board>; >> +            #clock-cells = <0x1>; >> +            #reset-cells = <0x1>; > 0x1 -> 1, it's a number and not a register Thanks for pointing it out, will fix it in next spin. > > Konrad