[PATCH 1/6] arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node

[PATCH 1/6] arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node

[Macpaul Lin]

The infracfg_ao node in mt8195.dtsi was causing a dtbs_check error.
The error message was:

syscon@10001000: compatible: ['mediatek,mt8195-infracfg_ao', 'syscon',
                 'simple-mfd'] is too long

To resolve this, remove 'simple-mfd' from the 'compatible' property of the
infracfg_ao node.

Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board")
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index e89ba384c4aa..2e1b41359b43 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -487,7 +487,7 @@ topckgen: syscon@10000000 {
 		};
 
 		infracfg_ao: syscon@10001000 {
-			compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
+			compatible = "mediatek,mt8195-infracfg_ao", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
-- 
2.45.2

[PATCH 2/6] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs

[Macpaul Lin]

The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due
to an excessively long 'interrupts' property. The error message was:

  infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0],
                     [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]]
                     is too long

To address this issue, add "minItems: 1" and "maxItems: 5" constraints to
the 'interrupts' property in the DT binding schema. This change allows for
flexibility in the number of interrupts for new SoCs

Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema")

Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index ea6b0f5f24de..a00f1f0045b1 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -96,7 +96,8 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 5
 
   clocks:
     items:
-- 
2.45.2

[PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[Macpaul Lin]

The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
to an excessively long 'clocks' property:
  display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long

To resolve this issue, add "maxItems: 3" to the 'clocks' property in
the DT schema.

Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,split.yaml     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
index e4affc854f3d..42d2d483cc29 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
@@ -57,6 +57,7 @@ properties:
   clocks:
     items:
       - description: SPLIT Clock
+    maxItems: 3
 
 required:
   - compatible
-- 
2.45.2

[PATCH 4/6] arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phy

[Macpaul Lin]

The ethernet-phy node in mt8395-genio-1200-evk.dts was triggering a
dtbs_check error. The error message was:
  eth-phy0@1: $nodename:0: 'eth-phy0@1' does not match
              '^ethernet-phy(@[a-f0-9]+)?$'
Fix this issue by replacing 'eth-phy' node to generic 'ethernet-phy'.

Fixes: f2b543a191b6 ("arm64: dts: mediatek: add device-tree for Genio 1200 EVK board")
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
index 1ef6262b65c9..b4b48eb93f3c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
@@ -187,7 +187,7 @@ mdio {
 		compatible = "snps,dwmac-mdio";
 		#address-cells = <1>;
 		#size-cells = <0>;
-		eth_phy0: eth-phy0@1 {
+		eth_phy0: ethernet-phy@1 {
 			compatible = "ethernet-phy-id001c.c916";
 			reg = <0x1>;
 		};
-- 
2.45.2

[PATCH 5/6] arm64: dts: mt8195: Fix dtbs_check error for mutex node

[Macpaul Lin]

The mutex node in mt8195.dtsi was triggering a dtbs_check error:
  mutex@1c101000: 'clock-names', 'reg-names' do not match any of the
                  regexes: 'pinctrl-[0-9]+'

This seems no need by inspecting the DT schemas and other reference boards,
so drop 'clock-names' and 'reg-names' in mt8195.dtsi.

Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1")
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 2e1b41359b43..ade685ed2190 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -3331,11 +3331,9 @@ &larb19 &larb21 &larb24 &larb25
 		mutex1: mutex@1c101000 {
 			compatible = "mediatek,mt8195-disp-mutex";
 			reg = <0 0x1c101000 0 0x1000>;
-			reg-names = "vdo1_mutex";
 			interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
 			clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
-			clock-names = "vdo1_mutex";
 			mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
 			mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
 		};
-- 
2.45.2

[PATCH 6/6] dt-bindings: display: mediatek: dpi: Add mt8195 support in power domains

[Macpaul Lin]

Add power domain binding to the mediatek DPI controller for MT8185.

The dpi node in mt8195.dtsi was triggering a dtbs_check error:
  dp-intf@1c113000: power-domains: False schema does not allow [[44, 18]]

Fixes: 5474d49b2f79 ("dt-bindings: display: mediatek: dpi: Add power domains")
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 3a82aec9021c..07acc8a76bfc 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -89,6 +89,7 @@ allOf:
                 - mediatek,mt6795-dpi
                 - mediatek,mt8173-dpi
                 - mediatek,mt8186-dpi
+                - mediatek,mt8195-dp-intf
     then:
       properties:
         power-domains: false
-- 
2.45.2

Re: [PATCH 1/6] arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node

[AngeloGioacchino Del Regno]

Il 24/09/24 12:31, Macpaul Lin ha scritto:
> The infracfg_ao node in mt8195.dtsi was causing a dtbs_check error.
> The error message was:
> 
> syscon@10001000: compatible: ['mediatek,mt8195-infracfg_ao', 'syscon',
>                   'simple-mfd'] is too long
> 
> To resolve this, remove 'simple-mfd' from the 'compatible' property of the
> infracfg_ao node.
> 
> Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board")
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[AngeloGioacchino Del Regno]

Il 24/09/24 12:31, Macpaul Lin ha scritto:
> The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
> to an excessively long 'clocks' property:
>    display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long
> 
> To resolve this issue, add "maxItems: 3" to the 'clocks' property in
> the DT schema.
> 
> Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
>   .../devicetree/bindings/display/mediatek/mediatek,split.yaml     | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> index e4affc854f3d..42d2d483cc29 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> @@ -57,6 +57,7 @@ properties:
>     clocks:
>       items:
>         - description: SPLIT Clock

That's at least confusing (granted that it works) - either add a description for
each clock and then set `minItems: 1` (preferred), or remove this "SPLIT Clock"
description and allow a maximum of 3 clocks.

Removing the description can be done - IMO - because "SPLIT Clock" is, well,
saying that the SPLIT block gets a SPLIT clock ... stating the obvious, anyway.

Cheers,
Angelo

> +    maxItems: 3
>   
>   required:
>     - compatible

Re: [PATCH 4/6] arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phy

[AngeloGioacchino Del Regno]

Il 24/09/24 12:31, Macpaul Lin ha scritto:
> The ethernet-phy node in mt8395-genio-1200-evk.dts was triggering a
> dtbs_check error. The error message was:
>    eth-phy0@1: $nodename:0: 'eth-phy0@1' does not match
>                '^ethernet-phy(@[a-f0-9]+)?$'
> Fix this issue by replacing 'eth-phy' node to generic 'ethernet-phy'.
> 
> Fixes: f2b543a191b6 ("arm64: dts: mediatek: add device-tree for Genio 1200 EVK board")
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 5/6] arm64: dts: mt8195: Fix dtbs_check error for mutex node

[AngeloGioacchino Del Regno]

Il 24/09/24 12:31, Macpaul Lin ha scritto:
> The mutex node in mt8195.dtsi was triggering a dtbs_check error:
>    mutex@1c101000: 'clock-names', 'reg-names' do not match any of the
>                    regexes: 'pinctrl-[0-9]+'
> 
> This seems no need by inspecting the DT schemas and other reference boards,
> so drop 'clock-names' and 'reg-names' in mt8195.dtsi.
> 
> Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1")
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 6/6] dt-bindings: display: mediatek: dpi: Add mt8195 support in power domains

[AngeloGioacchino Del Regno]

Il 24/09/24 12:31, Macpaul Lin ha scritto:
> Add power domain binding to the mediatek DPI controller for MT8185.
> 
> The dpi node in mt8195.dtsi was triggering a dtbs_check error:
>    dp-intf@1c113000: power-domains: False schema does not allow [[44, 18]]
> 
> Fixes: 5474d49b2f79 ("dt-bindings: display: mediatek: dpi: Add power domains")
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
>   .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml       | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> index 3a82aec9021c..07acc8a76bfc 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> @@ -89,6 +89,7 @@ allOf:
>                   - mediatek,mt6795-dpi
>                   - mediatek,mt8173-dpi
>                   - mediatek,mt8186-dpi
> +                - mediatek,mt8195-dp-intf

The dp_intf1 block has a power domain (VDOSYS1)... so that will break the check
for the other one.

Besides, I'm fairly sure that the right fix is to actually add the missing VDOSYS0
power domain to dp_intf0 instead, as that block is indeed in VDO0.

So.. for this patch: nak.

Cheers,
Angelo

>       then:
>         properties:
>           power-domains: false

Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[Conor Dooley]

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On Tue, Sep 24, 2024 at 01:42:01PM +0200, AngeloGioacchino Del Regno wrote:
> Il 24/09/24 12:31, Macpaul Lin ha scritto:
> > The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
> > to an excessively long 'clocks' property:
> >    display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long
> > 
> > To resolve this issue, add "maxItems: 3" to the 'clocks' property in
> > the DT schema.
> > 
> > Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > ---
> >   .../devicetree/bindings/display/mediatek/mediatek,split.yaml     | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > index e4affc854f3d..42d2d483cc29 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > @@ -57,6 +57,7 @@ properties:
> >     clocks:
> >       items:
> >         - description: SPLIT Clock
> 
> That's at least confusing (granted that it works) - either add a description for
> each clock and then set `minItems: 1` (preferred), or remove this "SPLIT Clock"
> description and allow a maximum of 3 clocks.
> 
> Removing the description can be done - IMO - because "SPLIT Clock" is, well,
> saying that the SPLIT block gets a SPLIT clock ... stating the obvious, anyway.

Right, but what are the other two new clocks? Are they as obvious?
There's no clock-names here to give any more information as to what the
other clocks are supposed to be.

Kinda unrelated, but I think that "SPLIT Clock" probably isn't what the
name of the clock in the IP block is anyway, sounds more like the name
for it on the provider end..

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Re: [PATCH 2/6] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs

[Conor Dooley]

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On Tue, Sep 24, 2024 at 06:31:52PM +0800, Macpaul Lin wrote:
> The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due
> to an excessively long 'interrupts' property. The error message was:
> 
>   infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0],
>                      [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]]
>                      is too long
> 
> To address this issue, add "minItems: 1" and "maxItems: 5" constraints to
> the 'interrupts' property in the DT binding schema. This change allows for
> flexibility in the number of interrupts for new SoCs
> 
> Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema")
> 

This space should be removed.

> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
>  Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index ea6b0f5f24de..a00f1f0045b1 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -96,7 +96,8 @@ properties:
>      maxItems: 1
>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 5

You need to add an items list here, and probably some per compatible
constraints. What are each of the itnerrupts for?

>  
>    clocks:
>      items:
> -- 
> 2.45.2
> 

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Re: [PATCH 6/6] dt-bindings: display: mediatek: dpi: Add mt8195 support in power domains

[Macpaul Lin]

On 9/24/24 19:48, AngeloGioacchino Del Regno wrote:

> Il 24/09/24 12:31, Macpaul Lin ha scritto:
>> Add power domain binding to the mediatek DPI controller for MT8185.
>> 
>> The dpi node in mt8195.dtsi was triggering a dtbs_check error:
>>    dp-intf@1c113000: power-domains: False schema does not allow [[44, 18]]
>> 
>> Fixes: 5474d49b2f79 ("dt-bindings: display: mediatek: dpi: Add power domains")
>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>> ---
>>   .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml       | 1 +
>>   1 file changed, 1 insertion(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
>> index 3a82aec9021c..07acc8a76bfc 100644
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
>> @@ -89,6 +89,7 @@ allOf:
>>                   - mediatek,mt6795-dpi
>>                   - mediatek,mt8173-dpi
>>                   - mediatek,mt8186-dpi
>> +                - mediatek,mt8195-dp-intf
> 
> The dp_intf1 block has a power domain (VDOSYS1)... so that will break the check
> for the other one.
> 
> Besides, I'm fairly sure that the right fix is to actually add the missing VDOSYS0
> power domain to dp_intf0 instead, as that block is indeed in VDO0.
> 
> So.. for this patch: nak.
> 
> Cheers,
> Angelo

Tommy and I was wondering why DP-INTF0 will work without power domain.
After lookup others node in the mt8195.dtsi, I guess this is because the 
power domain VDOSYS0 has been enabled by other modules.

However this patch is still required after adding power domain to DP-INTF0.
Otherwise the dpi errors will become two. :~
  dp-intf@1c015000: power-domains: False schema does not allow [[44, 16]]
  dp-intf@1c113000: power-domains: False schema does not allow [[44, 18]]

I'll send a separate patch to add VDOSYS0 for DP-INTF0.

Thanks
Macpaul Lin

Re: [PATCH 2/6] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs

[Macpaul Lin]

On 9/25/24 00:02, Conor Dooley wrote:
> On Tue, Sep 24, 2024 at 06:31:52PM +0800, Macpaul Lin wrote:
>> The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due
>> to an excessively long 'interrupts' property. The error message was:
>>
>>    infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0],
>>                       [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]]
>>                       is too long
>>
>> To address this issue, add "minItems: 1" and "maxItems: 5" constraints to
>> the 'interrupts' property in the DT binding schema. This change allows for
>> flexibility in the number of interrupts for new SoCs
>>
>> Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema")
>>
> 
> This space should be removed.

Thanks! Will fix it in the next version.

>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>> ---
>>   Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>> index ea6b0f5f24de..a00f1f0045b1 100644
>> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
>> @@ -96,7 +96,8 @@ properties:
>>       maxItems: 1
>>   
>>     interrupts:
>> -    maxItems: 1
>> +    minItems: 1
>> +    maxItems: 5
> 
> You need to add an items list here, and probably some per compatible
> constraints. What are each of the itnerrupts for?
> 

According to Friday Yang's comment,
The IOMMU of MT8195 has 5 banks: 0/1/2/3/4. Each bank has a set of APB 
registers
corresponding to the normal world, protected world 1/2/3,
and secure world, respectively.
Therefore, 5 interrupt numbers are needed.

>>   
>>     clocks:
>>       items:
>> -- 
>> 2.45.2
>>

Will try to fix it and add some description for MT8195.
I think this patch could be split as a separated patch from the origin
patch set. It'll take some time to refine the patch.

Thanks
Macpaul Lin

Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[Macpaul Lin]

On 9/25/24 00:00, Conor Dooley wrote:
> On Tue, Sep 24, 2024 at 01:42:01PM +0200, AngeloGioacchino Del Regno wrote:
>> Il 24/09/24 12:31, Macpaul Lin ha scritto:
>>> The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
>>> to an excessively long 'clocks' property:
>>>     display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long
>>>
>>> To resolve this issue, add "maxItems: 3" to the 'clocks' property in
>>> the DT schema.
>>>
>>> Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
>>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>>> ---
>>>    .../devicetree/bindings/display/mediatek/mediatek,split.yaml     | 1 +
>>>    1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>> index e4affc854f3d..42d2d483cc29 100644
>>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>> @@ -57,6 +57,7 @@ properties:
>>>      clocks:
>>>        items:
>>>          - description: SPLIT Clock
>>
>> That's at least confusing (granted that it works) - either add a description for
>> each clock and then set `minItems: 1` (preferred), or remove this "SPLIT Clock"
>> description and allow a maximum of 3 clocks.
>>
>> Removing the description can be done - IMO - because "SPLIT Clock" is, well,
>> saying that the SPLIT block gets a SPLIT clock ... stating the obvious, anyway.
> 
> Right, but what are the other two new clocks? Are they as obvious?
> There's no clock-names here to give any more information as to what the
> other clocks are supposed to be.
> 
> Kinda unrelated, but I think that "SPLIT Clock" probably isn't what the
> name of the clock in the IP block is anyway, sounds more like the name
> for it on the provider end..

Thanks for the suggestions. I think Moudy could help on the new fixes
for both DT schem and mt8195.dtsi. This patch could be separated from
origin patch set.

Thanks
Macpaul Lin

Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[Conor Dooley]

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On Wed, Sep 25, 2024 at 04:42:59PM +0800, Macpaul Lin wrote:
> 
> On 9/25/24 00:00, Conor Dooley wrote:
> > On Tue, Sep 24, 2024 at 01:42:01PM +0200, AngeloGioacchino Del Regno wrote:
> > > Il 24/09/24 12:31, Macpaul Lin ha scritto:
> > > > The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
> > > > to an excessively long 'clocks' property:
> > > >     display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long
> > > > 
> > > > To resolve this issue, add "maxItems: 3" to the 'clocks' property in
> > > > the DT schema.
> > > > 
> > > > Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
> > > > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > > > ---
> > > >    .../devicetree/bindings/display/mediatek/mediatek,split.yaml     | 1 +
> > > >    1 file changed, 1 insertion(+)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > > > index e4affc854f3d..42d2d483cc29 100644
> > > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > > > @@ -57,6 +57,7 @@ properties:
> > > >      clocks:
> > > >        items:
> > > >          - description: SPLIT Clock
> > > 
> > > That's at least confusing (granted that it works) - either add a description for
> > > each clock and then set `minItems: 1` (preferred), or remove this "SPLIT Clock"
> > > description and allow a maximum of 3 clocks.
> > > 
> > > Removing the description can be done - IMO - because "SPLIT Clock" is, well,
> > > saying that the SPLIT block gets a SPLIT clock ... stating the obvious, anyway.
> > 
> > Right, but what are the other two new clocks? Are they as obvious?
> > There's no clock-names here to give any more information as to what the
> > other clocks are supposed to be.
> > 
> > Kinda unrelated, but I think that "SPLIT Clock" probably isn't what the
> > name of the clock in the IP block is anyway, sounds more like the name
> > for it on the provider end..
> 
> Thanks for the suggestions. I think Moudy could help on the new fixes
> for both DT schem and mt8195.dtsi. This patch could be separated from
> origin patch set.

Not sure what you mean about separating it, if you mean correcting the
description for the split clock sure. The other stuff I mentioned needs
to be resolved before I'm willing to ack this.

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Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[AngeloGioacchino Del Regno]

Il 25/09/24 16:34, Conor Dooley ha scritto:
> On Wed, Sep 25, 2024 at 04:42:59PM +0800, Macpaul Lin wrote:
>>
>> On 9/25/24 00:00, Conor Dooley wrote:
>>> On Tue, Sep 24, 2024 at 01:42:01PM +0200, AngeloGioacchino Del Regno wrote:
>>>> Il 24/09/24 12:31, Macpaul Lin ha scritto:
>>>>> The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
>>>>> to an excessively long 'clocks' property:
>>>>>      display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long
>>>>>
>>>>> To resolve this issue, add "maxItems: 3" to the 'clocks' property in
>>>>> the DT schema.
>>>>>
>>>>> Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
>>>>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>>>>> ---
>>>>>     .../devicetree/bindings/display/mediatek/mediatek,split.yaml     | 1 +
>>>>>     1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>>>> index e4affc854f3d..42d2d483cc29 100644
>>>>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>>>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>>>>> @@ -57,6 +57,7 @@ properties:
>>>>>       clocks:
>>>>>         items:
>>>>>           - description: SPLIT Clock
>>>>
>>>> That's at least confusing (granted that it works) - either add a description for
>>>> each clock and then set `minItems: 1` (preferred), or remove this "SPLIT Clock"
>>>> description and allow a maximum of 3 clocks.
>>>>
>>>> Removing the description can be done - IMO - because "SPLIT Clock" is, well,
>>>> saying that the SPLIT block gets a SPLIT clock ... stating the obvious, anyway.
>>>
>>> Right, but what are the other two new clocks? Are they as obvious?
>>> There's no clock-names here to give any more information as to what the
>>> other clocks are supposed to be.
>>>
>>> Kinda unrelated, but I think that "SPLIT Clock" probably isn't what the
>>> name of the clock in the IP block is anyway, sounds more like the name
>>> for it on the provider end..
>>
>> Thanks for the suggestions. I think Moudy could help on the new fixes
>> for both DT schem and mt8195.dtsi. This patch could be separated from
>> origin patch set.
> 
> Not sure what you mean about separating it, if you mean correcting the
> description for the split clock sure. The other stuff I mentioned needs
> to be resolved before I'm willing to ack this.

He means separating this patch from the rest of the series that he pushed - which
is okay, as it's a bit mixed anyway :-)

Besides ... Moudy, can you please help to clarify the description of those clocks?

Cheers,
Angelo

Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[Moudy Ho (何宗原)]

On Thu, 2024-09-26 at 11:38 +0200, AngeloGioacchino Del Regno wrote:
> Il 25/09/24 16:34, Conor Dooley ha scritto:
> > On Wed, Sep 25, 2024 at 04:42:59PM +0800, Macpaul Lin wrote:
> > > 
> > > On 9/25/24 00:00, Conor Dooley wrote:
> > > > On Tue, Sep 24, 2024 at 01:42:01PM +0200, AngeloGioacchino Del
> > > > Regno wrote:
> > > > > Il 24/09/24 12:31, Macpaul Lin ha scritto:
> > > > > > The display node in mt8195.dtsi was triggering a CHECK_DTBS
> > > > > > error due
> > > > > > to an excessively long 'clocks' property:
> > > > > >      display@14f06000: clocks: [[31, 14], [31, 43], [31,
> > > > > > 44]] is too long
> > > > > > 
> > > > > > To resolve this issue, add "maxItems: 3" to the 'clocks'
> > > > > > property in
> > > > > > the DT schema.
> > > > > > 
> > > > > > Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp:
> > > > > > split each block to individual yaml")
> > > > > > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > > > > > ---
> > > > > >     .../devicetree/bindings/display/mediatek/mediatek,split
> > > > > > .yaml     | 1 +
> > > > > >     1 file changed, 1 insertion(+)
> > > > > > 
> > > > > > diff --git
> > > > > > a/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > ek,split.yaml
> > > > > > b/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > ek,split.yaml
> > > > > > index e4affc854f3d..42d2d483cc29 100644
> > > > > > ---
> > > > > > a/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > ek,split.yaml
> > > > > > +++
> > > > > > b/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > ek,split.yaml
> > > > > > @@ -57,6 +57,7 @@ properties:
> > > > > >       clocks:
> > > > > >         items:
> > > > > >           - description: SPLIT Clock
> > > > > 
> > > > > That's at least confusing (granted that it works) - either
> > > > > add a description for
> > > > > each clock and then set `minItems: 1` (preferred), or remove
> > > > > this "SPLIT Clock"
> > > > > description and allow a maximum of 3 clocks.
> > > > > 
> > > > > Removing the description can be done - IMO - because "SPLIT
> > > > > Clock" is, well,
> > > > > saying that the SPLIT block gets a SPLIT clock ... stating
> > > > > the obvious, anyway.
> > > > 
> > > > Right, but what are the other two new clocks? Are they as
> > > > obvious?
> > > > There's no clock-names here to give any more information as to
> > > > what the
> > > > other clocks are supposed to be.
> > > > 
> > > > Kinda unrelated, but I think that "SPLIT Clock" probably isn't
> > > > what the
> > > > name of the clock in the IP block is anyway, sounds more like
> > > > the name
> > > > for it on the provider end..
> > > 
> > > 
 * Thanks for the suggestions. I think Moudy could help on the new
   fixes
> > > for both DT schem and mt8195.dtsi. This patch could be separated
> > > from
> > > origin patch set.
> > 
> > Not sure what you mean about separating it, if you mean correcting
> > the
> > description for the split clock sure. The other stuff I mentioned
> > needs
> > to be resolved before I'm willing to ack this.
> 
> He means separating this patch from the rest of the series that he
> pushed - which
> is okay, as it's a bit mixed anyway :-)
> 
> Besides ... Moudy, can you please help to clarify the description of
> those clocks?
> 
> Cheers,
> Angelo

Greetings,

May I address the check error by adding 2 functional descriptions and
specifying 'minIeims: 1' for this property, and apply the limit by
setting 'maxItems: 3' in MT8195 additional condition?

Sincerely,
Moudy Ho

Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count constraint for new SoCs

[Conor Dooley]

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On Fri, Sep 27, 2024 at 02:27:14AM +0000, Moudy Ho (何宗原) wrote:
> On Thu, 2024-09-26 at 11:38 +0200, AngeloGioacchino Del Regno wrote:
> > Il 25/09/24 16:34, Conor Dooley ha scritto:
> > > On Wed, Sep 25, 2024 at 04:42:59PM +0800, Macpaul Lin wrote:
> > > > 
> > > > On 9/25/24 00:00, Conor Dooley wrote:
> > > > > On Tue, Sep 24, 2024 at 01:42:01PM +0200, AngeloGioacchino Del
> > > > > Regno wrote:
> > > > > > Il 24/09/24 12:31, Macpaul Lin ha scritto:
> > > > > > > The display node in mt8195.dtsi was triggering a CHECK_DTBS
> > > > > > > error due
> > > > > > > to an excessively long 'clocks' property:
> > > > > > >      display@14f06000: clocks: [[31, 14], [31, 43], [31,
> > > > > > > 44]] is too long
> > > > > > > 
> > > > > > > To resolve this issue, add "maxItems: 3" to the 'clocks'
> > > > > > > property in
> > > > > > > the DT schema.
> > > > > > > 
> > > > > > > Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp:
> > > > > > > split each block to individual yaml")
> > > > > > > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > > > > > > ---
> > > > > > >     .../devicetree/bindings/display/mediatek/mediatek,split
> > > > > > > .yaml     | 1 +
> > > > > > >     1 file changed, 1 insertion(+)
> > > > > > > 
> > > > > > > diff --git
> > > > > > > a/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > > ek,split.yaml
> > > > > > > b/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > > ek,split.yaml
> > > > > > > index e4affc854f3d..42d2d483cc29 100644
> > > > > > > ---
> > > > > > > a/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > > ek,split.yaml
> > > > > > > +++
> > > > > > > b/Documentation/devicetree/bindings/display/mediatek/mediat
> > > > > > > ek,split.yaml
> > > > > > > @@ -57,6 +57,7 @@ properties:
> > > > > > >       clocks:
> > > > > > >         items:
> > > > > > >           - description: SPLIT Clock
> > > > > > 
> > > > > > That's at least confusing (granted that it works) - either
> > > > > > add a description for
> > > > > > each clock and then set `minItems: 1` (preferred), or remove
> > > > > > this "SPLIT Clock"
> > > > > > description and allow a maximum of 3 clocks.
> > > > > > 
> > > > > > Removing the description can be done - IMO - because "SPLIT
> > > > > > Clock" is, well,
> > > > > > saying that the SPLIT block gets a SPLIT clock ... stating
> > > > > > the obvious, anyway.
> > > > > 
> > > > > Right, but what are the other two new clocks? Are they as
> > > > > obvious?
> > > > > There's no clock-names here to give any more information as to
> > > > > what the
> > > > > other clocks are supposed to be.
> > > > > 
> > > > > Kinda unrelated, but I think that "SPLIT Clock" probably isn't
> > > > > what the
> > > > > name of the clock in the IP block is anyway, sounds more like
> > > > > the name
> > > > > for it on the provider end..
> > > > 
> > > > 
>  * Thanks for the suggestions. I think Moudy could help on the new
>    fixes
> > > > for both DT schem and mt8195.dtsi. This patch could be separated
> > > > from
> > > > origin patch set.
> > > 
> > > Not sure what you mean about separating it, if you mean correcting
> > > the
> > > description for the split clock sure. The other stuff I mentioned
> > > needs
> > > to be resolved before I'm willing to ack this.
> > 
> > He means separating this patch from the rest of the series that he
> > pushed - which
> > is okay, as it's a bit mixed anyway :-)
> > 
> > Besides ... Moudy, can you please help to clarify the description of
> > those clocks?
> 
> May I address the check error by adding 2 functional descriptions and
> specifying 'minIeims: 1' for this property, and apply the limit by
> setting 'maxItems: 3' in MT8195 additional condition?


That sounds reasonable

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