From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBE7DF9E4; Mon, 15 Jan 2024 10:22:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="CnDVwwWv" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40FAMe6H076580; Mon, 15 Jan 2024 04:22:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705314160; bh=nchkyYLXFwGmpBMKfp4fgZvkM2ImjBBZRWySCFCmsQo=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=CnDVwwWvcrNtkMsn95bGYFjySfe6kU4DxQG5dmPrf1g3kopJ3JFwLSs3YFWCzciIn EAlk6XLlg8vFqedw8isFzfLkjfF2rwDVGx3OZFRMVT/iN8vyozx7MitOHgfJ0Urpt4 wmNdBTyQp6zeRrATEZyG70bpEFtDB041nnxfvres= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40FAMeSR119693 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jan 2024 04:22:40 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jan 2024 04:22:40 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jan 2024 04:22:39 -0600 Received: from [172.24.20.156] (lt5cd2489kgj.dhcp.ti.com [172.24.20.156]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40FAMaFc066164; Mon, 15 Jan 2024 04:22:37 -0600 Message-ID: <45b833bf-e568-4b8f-93f2-07340e794b6c@ti.com> Date: Mon, 15 Jan 2024 15:52:35 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: ti: Add support for TI J722S Evaluation Module To: Vaishnav Achath , , , , , , , , CC: , , References: <20231213124930.3012-1-vaishnav.a@ti.com> <20231213124930.3012-4-vaishnav.a@ti.com> Content-Language: en-US From: "Kumar, Udit" In-Reply-To: <20231213124930.3012-4-vaishnav.a@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hi Vaishnav On 12/13/2023 6:19 PM, Vaishnav Achath wrote: > Add basic support for the J722S EVM with UART console and > MMC SD as rootfs. > > Schematics are available at: > https://www.ti.com/lit/zip/sprr495 > > Co-developed-by: Jayesh Choudhary > Signed-off-by: Jayesh Choudhary > Signed-off-by: Vaishnav Achath > --- > [..] > + > + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { > + compatible = "shared-dma-pool"; > + reg = <0x00 0xa0100000 0x00 0xf00000>; > + no-map; > + }; Do you think, we should have someĀ  reserve memory for dma area as well Something like wkup_r5fss0_core0_dma_memory_region > + > + }; > + [..]