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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e On 10/21/26 09:55, Florian Fainelli wrote: > This patch series fixes SATA on the Northstar Plus (BCM58xxx/8831x) > which was broken due to a number of things: > > - the SATA PHY assumed separate PCB windows when a shared one is used > for this generation of SoCs > - the clock/reset (IDM) was not being configured by the driver which > meant that depending upon what the boot loader did, or did not, we > could have had the AHCI controller still in reset by then > - on some reference boards, the AHCI controller is not DMA coherent, > assuming so leads to all sorts of timeouts, data corruption, etc. > > Since this touches several subsystems: DT, PHY, AHCI and DTS, I would be > keen on having Damien merge all of those via his tree if acceptable by > the DT and PHY maintainers, I am OK either way for Broadcom SoC. Argh, looks like I submitted patches 5 and 6 twice after I had re-ordered them, the correct order is in the cover letter: ARM: dts: broadcom: Use noncoherent SATA DMA on BCM958625HR ARM: dts: broadcom: Enable SATA on BCM958625HR Will wait for feedback and resubmit if necessary. Thanks! -- Florian